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Registered: ‎06-15-2017

Kintex UltraScale - upowered IOB, ESD protection, sequencing

Hi All,


I'd like to ask you for an assurance of my design intentions.


1) Firstly, I'd like to know what the structure of the ESD protection at the IO pins in HP/HR bank is.

Are there present conventional ESD diodes connected to GND and VCCIO ?



2) The product I'm developing is a board with XCKU060 FPGA whose two HR IOBs are connected to a microcontroller via a quite wide bus (~ 50 to 70 IOs) where approximately a half of the IOs are MCU outputs. There is a possiblity that the FPGA could be completely  unpowered for extended periods of time, while the MCU would drive the IOs.


My concern is the current that might flow thru the ESD diode to the VCCIO rail of the FPGA and thus "try to power" the FPGA IOB and other peripherals powered from the same rail, excessively loading the MCU outputs...


The apparent solution is to permanently power the IOB by e.g. OR-ing the power rails of the FPGA supply with the supply of the MCU via some ideal diode etc. I've already used that successfully with different FPGA family.


As far as I've found out, there isn't a requirement (unlinke for the Kintex-7 family in case of the 3.3 VCCIO) that the HR IOB cannot be permanently powered by 3.3V while rest of the FPGA rails are disconnected/powered-off. Moreover, I've found on this forum that the recommended power-on/off sequence isn't that strict so if there is any forbidden sequence, it would be stated in the device datasheet.



Can the HR bank of the Kintex UltraScale be permanently powered by 3.3 V even if the rest of the FPGA is unpowered ?


Thank you very much for you opinion





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2 Replies
Community Manager
Community Manager
Registered: ‎08-08-2007

This AR should be of some help :




Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub , Versal Blogs and the Versal Useful Resources .

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Registered: ‎02-27-2008



1.  The IO structure has the intrinsic (body diodes) of the CMOS output driver always present.  So, yes, there is a diode to Vcco, and a diode from ground, to the IO pin.


2.  An unpowered IO bank requires as little as 2 mA to power on, so the ESD diodes easily power on the Vcco of that bank.


As long as the abs max spec is not exceeded, there is no damage.



Austin Lesea
Principal Engineer
Xilinx San Jose
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