11-01-2019 12:14 PM
Can SelectIO pin outputs ever drive high/low when VCCO is powered on (eg. @ 1.0-1.8V) while all other device power rails are not powered?
Or is this impossible to predict because there are memory/configuration elements in the bank powered solely by VCCO that come up in an indeterminate state, hence the output could be tristate/driving-low/driving-high depending on chance?
My situation is another back-powered-VCCO-type, but this precise clarification does not seem to have been sought before.
(and I don’t know where I can find a representative internal circuit diagram of SelectIO with references to VCCO and where the IO configuration states are latched / what power supply they are on). I have also read AR# 37347, 45985, 65036, etc.
I have a sub-LVDS level signal (max: ~1.1V DC to GND) continuously present on the device pins while the device is otherwise completely unpowered. (Obviously the SelectIO will not be configured in sub-LVDS mode at this time).
Unfortunately my sub-LVDS signals cannot be AC-coupled or turned off at their source. So the only solution I can see if the device cannot handle this condition is to add a fairly undesirable series isolation circuit to these ~1Gbps lines.
It seems to follow that the VCCO of this bank will be back-powered through clamp diodes at a worst case level of around 1.1-0.4= ~0.7V.
Which is less than the minimum 0.95V recommended operating condition on HP banks, but there is enough source drive strength to provide the ~2mA required for bank power up stated in other topics on this forum.
Given this powered-up bank state and all other device supplies at 0V, is it possible that some of the other pins on this bank will:
(1). Drive to GND (quite bad in my case – ‘shorting’ those sub-LVDS lines to GND), or
(2). Drive to the VCCO level (not very bad – would just pull VCCO up to ~1.1V), or
(3). Remain relatively “tristate” even though some/all of them are actually sinking a little current through their clamp diodes to VCCO (this would be fine so long as the device can handle this indefinitely).
The answer in AR# 45985 makes me think it might be (3) that happens in the 7-series HR banks, as the answer considers up to 10x pins back-powering VCCO but doesn’t consider that one of those output drivers might turn on and try pulling the 3.3V input to GND - potentially sinking a lot of current.
Thank you for any insight you can provide.
11-12-2019 03:56 AM
The Kintex UltraScale DS has a section on Power Sequencing
"The recommended power-on sequence is VCCINT/VCCINT_IO, VCCBRAM, VCCAUX/VCCAUX_IO, and VCCO to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. "
Other sequences will not damage the device but the functionality is not guaranteed. When you start your power sequence you may see unintended behavior on the IOs as the Vcco it on before the Vccint.
The Vin is Vcco + 0.2V if Vcco is not powered the Vin should be no more than 0.2V, or you will forward bias the clamp diode and need to adhere to the Iin spec.
I would not expect (though there are no guarantees when you are operating outside the recommended seqeuence) that this back-powered-up bank will to try to drive Vcco or GND as the IOs are not yet configured (so they are not yet input or output). Though when you do power on the device it would be very possible to see glitches on the lines.