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Contributor
Contributor
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Registered: ‎05-27-2008

MIPI RX and SUB_LVDS RX in same ZUS+ HP Bank

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Placing a MIPI CSI RX IP core in a ZUS+ HP bank sets the bank VCCO to 1.2V and enables internal 100 Ohm termination and DCI on MIPI inputs.  I can also add SUB_LVDS inputs in the same bank.  Can I enable internal 100 Ohm termination for the SUB_LVDS inputs by using the following XDC command?

   set_property DIFF_TERM_ADV TERM_100 [get_ports SUB_LVDS_PORT_NAME]  

My concern is that the MIPI and SUB_LVDS use different VCCOs (1.2V vs 1.8V). But, since I'm only working with inputs, does the VCCO difference matter?

jd
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Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

Hi @pburrell 

Enabling DIFF_TERM for SUB-LVDS with VCCO=1.2V is not recommended. It is recommended to use external termination in such case. Please follow note 1 provided below Table 1-77:VCCO and VREF Requirements for Each Supported I/O Standard in UG571 (v1.12).

We did not characterize such scenario. So, we cannot comment on its effects.

Internal termination resistor is nothing but Silicon transistor and its characteristics dependent upon VCCO provided to the FPGA Bank. You must follow Table 1-77:VCCO and VREF Requirements for Each Supported I/O Standard.

Regards,
Bhushan

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Contributor
Contributor
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Registered: ‎05-27-2008
These three questions do a better job of summarizing what we are looking for:

I think we can sum it up to a couple of key questions…..

1. Can the input MIPI D-PHY termination be turned off (if it is really on). This would allow me to put permanent external resistors
2. Can SubLVDS inputs be used on the HP bank running at 1.2V VCCO with external termination? – Think that this is yes, but should confirm.
3. Can SubLVDS input termination (100 Ohm) be turned on at 1.2V VCCO?
jd
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Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

Hi @jdehaven 

  • Can the input MIPI D-PHY termination be turned off (if it is really on). This would allow me to put permanent external resistors
    • Based on attribute MIPI_DPHY_DCI I/O standard provided in UG571 (v1.12); input termination is disabled by default.

bpatil_0-1596785327062.png

 

  • Can SubLVDS inputs be used on the HP bank running at 1.2V VCCO with external termination? – Think that this is yes, but should confirm.
    • Yes, you are correct.
    • Please check notes provided below Table 1-77:VCCO and VREF Requirements for Each Supported I/O Standard in UG571 (v1.12).

bpatil_1-1596785327074.png

 

  • Can SubLVDS input termination (100 Ohm) be turned on at 1.2V VCCO?
    • No. This is not recommended. It is recommended to use external termination. Please follow note 1 provided below Table 1-77:VCCO and VREF Requirements for Each Supported I/O Standard in UG571 (v1.12).
Regards,
Bhushan

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @jdehaven ,
#Just adding my two cents.

1. If you are using Xilinx MIPI D-PHY RX or MIPI CSI-2 RX Subsystem with Vivado 2018.3 or later.
    DIFF_TERM_ADV is enabled by default.
2.  You can check your IO ports implementation result to confirm if DIFF_TERM_ADV is enabled.
    DIFF_TERM_ADV_enabled.png
3. You can manually enabled or disabled ( not recommended tough) by using the following tcl command

set_property DIFF_TERM_ADV TERM_100  [get_ports <data_rxp[*]/n[*]>]
set_property DIFF_TERM_ADV TERM_NONE [get_ports <data_rxp[*]/n[*]>]


Thanks
Leo

 

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Visitor
Visitor
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Registered: ‎08-05-2013

Just curious, if you have VCCO set at 1.2V and a Sub-LVDS signal and you turned on 100 ohm termination, what is expected to happen? Something other than it doesn't work.

   

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello,

This may damage your FPGA pins if you have 1.8V input. See also Table 1 of your device datasheet.
datasheet_VIN_VCCO.png

Thanks
Leo

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Visitor
Visitor
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Registered: ‎08-05-2013

SubLVDS is a reduced voltage version of LVDS.   Instead of 1.2V common mode  with 400mV signal, it is 900mv bias with the 400mv signal.   This is definitely below the max voltage specified above of 1.75V.    Even LVDS is below that, but 300mV of margin is not as good as one might like.   SubLVDS gives you 675mV of margin.

The concern I have is how is the termination done?   If it is DCI based, then having a lower VCCO might change the termination.  If it is actively driving, how does the lower value affect the expected termination equivalent?   Also, does a lower VCCO change the threshold values of the input?

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

Hi @pburrell 

Enabling DIFF_TERM for SUB-LVDS with VCCO=1.2V is not recommended. It is recommended to use external termination in such case. Please follow note 1 provided below Table 1-77:VCCO and VREF Requirements for Each Supported I/O Standard in UG571 (v1.12).

We did not characterize such scenario. So, we cannot comment on its effects.

Internal termination resistor is nothing but Silicon transistor and its characteristics dependent upon VCCO provided to the FPGA Bank. You must follow Table 1-77:VCCO and VREF Requirements for Each Supported I/O Standard.

Regards,
Bhushan

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Give Kudos to a post which you think is helpful and reply oriented.
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