11-16-2018 10:44 AM
Hello, I've been using Altera FPGA's for a long time and have noticed that Altera's newer FPGAs do not support 3.3V IO. Are Xilinx FPGA also moving away from 3.3V IO?
11-16-2018 12:28 PM
Our newest family is the Zynq UltraScale+ MPSoC and there are three types of banks, the HP, HD and MIO.
The HD and MIO banks support 3.3V : http://www.xilinx.com/support/documentation/data_sheets/ds925-zynq-ultrascale-plus.pdf
11-16-2018 12:35 PM
Hi, thanks for responding to my post. That is very good news. With Altera's new FPGA's I would have to put a ton of voltage translators on my board.
Have a great day.
11-16-2018 01:30 PM
From here you should read carefully the Ultrascale Select-IO User Guide and the Zynq TRM.
As you proceed be sure to understand that the MIO pins will enable you to interface with peripherals from the processor sub system. The MIO do support 3.3V signalling but not every peripheral is 3.3V.
On the FPGA side the HD bank does support 3.3V signalling but there are limitations on the available IO STANDARDS, some restriction on clocking (there is no clock managment tile adjacent to the bank for example). A maximum data rate of 250Mbps is supported. HDIO is intended for low speed control and status signals.
11-19-2018 08:47 AM
So if you look at the package overview section in UG575 you see the conceptual diagram of each VUP device.
In this case you can see we only support HP banks. there is no version of Virtex Ultrascale+ that supports HD banks.