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mildred
Visitor
Visitor
266 Views
Registered: ‎03-22-2021

ODELAYE3 var_load unconsitency

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Hello,

In one answer record the cntvaluein calculation is described by the following procedure:

  1. Start with EN_VTC = 1
  2. Program initial DELAY_VALUE to be a non-zero FIXED value, DLY0
  3. In order to switch to the new DELAY, DLY1 using the VAR_LOAD mode do the following:

    • De-assert EN_VTC. Wait 10 CLKDIV cycles.
    • Read CNTVALUEOUT of I/ODELAY
    • Load CNTVALUEIN = CNTVALUEOUT * (DLY1/DLY0)
    • Wait 10 CLKDIV cycles. Re-assert EN_VTC

https://www.xilinx.com/support/answers/60802.html

In the other one this what is described:

  1. Start with EN_VTC = 1
  2. Program initial DELAY_VALUE to be a non-zero FIXED value, DLY0
  3. In order to switch to the new DELAY, DLY1 using the VAR_LOAD mode do the following:
    1. De-assert EN_VTC. Wait 10 CLKDIV cycles.
    2. Read CNTVALUEOUT of I/ODELAY
    3. Load CNTVALUEIN = ((CNTVALUEOUT -54) * (DLY1/DLY0))+54
              For example, DLY0 = 500 and CNTVALEUOUT= 154
              The new required DLY1 = 520
              CNTVALUEIN = ((154-54)*(520/500))+54 = 158
    4. Wait 10 CLKDIV cycles. Re-assert EN_VTC

https://www.xilinx.com/support/answers/66013.html

Which is the correct one?

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pthakare
Moderator
Moderator
187 Views
Registered: ‎08-08-2017

Hi @mildred 

The intrinsic delay is not accounted in above calculation .

In simulation the intrinsic delay is fixed  (200ps).

In order check exact intrinsic delay Set the DELAY_VALUE =0 , constraint your I/O interface ,perform the synthesis  and check the tpd (prorogation delay) of ODELAYE3 in static timing analysis .

While performing the calculation for DLY1 you need to consider this intrinsic delay .  

i.e   DLY1 (considering intrinsic delay) =   DLY1 - Intrinsic delay.

 

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3 Replies
pthakare
Moderator
Moderator
214 Views
Registered: ‎08-08-2017

Hi @mildred 

Looking at the tilte , your query is specific to ODELAYE3 and not for both (IDELAYE3 and ODELAYE3). right ?

Can you please also specify if you want to use DELAY_FORMAT= TIME or COUNT?

For ODELAYE3 , The below procedure  in https://www.xilinx.com/support/answers/60802.html  is correct 

  1. Start with EN_VTC = 1
  2. Program initial DELAY_VALUE to be a non-zero FIXED value, DLY0
  3. In order to switch to the new DELAY, DLY1 using the VAR_LOAD mode do the following:

    • De-assert EN_VTC. Wait 10 CLKDIV cycles.
    • Read CNTVALUEOUT of I/ODELAY
    • Load CNTVALUEIN = CNTVALUEOUT * (DLY1/DLY0)
    • Wait 10 CLKDIV cycles. Re-assert EN_VTC

 

For the IDELAYE3 we need to consider clock alignment delay if DELAY_FORMAT = TIME . In this case the procedure in https://www.xilinx.com/support/answers/66013.html is correct .

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------
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mildred
Visitor
Visitor
201 Views
Registered: ‎03-22-2021

Hello, thanks for your reply

I want to use ODELAYE3  in TIME mode and VAR_LOAD mode with an IDELAYCTRL.

I use this procedure:

  1. Start with EN_VTC = 1
  2. Program initial DELAY_VALUE to be a non-zero FIXED value, DLY0
  3. In order to switch to the new DELAY, DLY1 using the VAR_LOAD mode do the following:

    • De-assert EN_VTC. Wait 10 CLKDIV cycles.
    • Read CNTVALUEOUT of I/ODELAY
    • Load CNTVALUEIN = CNTVALUEOUT * (DLY1/DLY0)
    • Wait 10 CLKDIV cycles. Re-assert EN_VTC

But in simulation i find a 200 ps offset between signal datain and signal dataout compared to my desired delay DLY1. I read that it was the intrinsic delay but i thought that the procedure above enabled us to account for the intrinsic delay. Therefore i still don't understand how to achieve a desired DLY1 in ps with the DELAY_FORMAT= TIME in VAR_LOAD mode. My aim is to delay a signal by a precise and constant amount in pico seconds

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pthakare
Moderator
Moderator
188 Views
Registered: ‎08-08-2017

Hi @mildred 

The intrinsic delay is not accounted in above calculation .

In simulation the intrinsic delay is fixed  (200ps).

In order check exact intrinsic delay Set the DELAY_VALUE =0 , constraint your I/O interface ,perform the synthesis  and check the tpd (prorogation delay) of ODELAYE3 in static timing analysis .

While performing the calculation for DLY1 you need to consider this intrinsic delay .  

i.e   DLY1 (considering intrinsic delay) =   DLY1 - Intrinsic delay.

 

-------------------------------------------------------------------------------------------------------------------------------
Reply if you have any queries, give kudos and accept as solution
-------------------------------------------------------------------------------------------------------------------------------

View solution in original post