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feka
Observer
Observer
10,275 Views
Registered: ‎02-12-2013

PCI Express Device Control register of each SRIOV function.

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Hello

 

I am trying to design with UltraScale Architecture Gen3 Integrated Block for PCI Express.

I can't find capability to get Device Control register of each SRIOV function.

As I understand Configuration Status Interface provides only information about Physical function 0.

Also there is Per Function Status Interface, but what function it belongs to isn't clear.

When I configure my PC driver to enable SRIOV I see that Virtual and Physical Functions are configured

with different MPS and MRR. And I don't know how to get their MPS and MRR on hardware side.

 

So, my question is how to access configuration space inside integrated block from user logic to get MPS and MRR for each

Physical and Virtual functions?

 

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feka
Observer
Observer
19,366 Views
Registered: ‎02-12-2013

Ok.

 

As I understand there is no necessity to know MPS of VFs and PFs with non-zero numbers.

The only Root Complex, that can generate SRIOV traffic is PC, and PC can't generate read requests with

dwords count more than minimal possible MPS (128 bytes).  So there is no need hardware to track MPS of VFs transactions.

 

So the only case when Hardware need to complete read request with splited TLPs is read request to PF 0 from another endpoint.

 

 

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feka
Observer
Observer
19,367 Views
Registered: ‎02-12-2013

Ok.

 

As I understand there is no necessity to know MPS of VFs and PFs with non-zero numbers.

The only Root Complex, that can generate SRIOV traffic is PC, and PC can't generate read requests with

dwords count more than minimal possible MPS (128 bytes).  So there is no need hardware to track MPS of VFs transactions.

 

So the only case when Hardware need to complete read request with splited TLPs is read request to PF 0 from another endpoint.

 

 

View solution in original post

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