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vanlandingham10
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Registered: ‎11-29-2017

POR Requirement with PS and PL Power up together.

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Hi,

I am currently in prototype phase and I am asking for clarification on the PS Reset Assertion Timing Requirements (Tpspor) and how they are applicable to the PL Configuration Switching Characteristics (Tpor). In the data sheet for the Zynq UltraScale+ MPSoC [DS925 (v1.16)] I see in table 37 the Required PS_POR_B assertion time is a min of 10 us. But the note below the table says:

"PS_POR_B must be asserted Low at power-up and continue to be asserted for a duration of TPSPOR after all the PS supply voltages reach
minimum levels. PS_POR_B must be asserted Low for the duration of TPOR when the PS and PL power-up at the same time and the
application uses both the PS and PL after power-up."

Okay, so I navigate to table 129 Configuration Switching Characteristics for the PL Power-up Timing Characteristics. There I find the Tpor where it specifies the max time it could take for the PL to configure with and without POROVERRIDE enabled and disable. It also specifies the assumed ramp time is within its specified time (2ms for override enabled and 40ms for override disabled). 

So I understand this as the following: 

If PL and PS are sharing voltages and come up at the same time then PS_POR_B must be asserted Low at power-up and continue to be asserted for a duration of not TPSPOR but rather TPOR (using the max value to guarantee the PL is ready to configure).

My confusion is that Note 1 of Table 37 makes me contridict myself as to when the TPOR specification begins since Table 129 says in note 1: 

"The TPOR specification begins when the last of the monitored supplies (VCCINT, VCCAUX, VCCBRAM) reaches 95% of its recommended
operating condition voltage."

Where Table 37 says it starts at the end of the last supply. Which is it? How long do I have to hold PS_POR_B low and when does that TPOR specification come into play?

"PS_POR_B must be asserted Low at power-up and continue to be asserted for a duration of TPSPOR after all the PS supply voltages reach
minimum levels."

I have attached my sequence diagram it would be helpful if you could help me find out from what sequence the TPOR specification starts.

Sequence Diagram.jpg
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gnarahar
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Registered: ‎07-23-2015

@vanlandingham10  Yes its 15ms if you having the 2ms ramp rate with POR override. Since your diagram had ">65ms" notation, I assumed you had the 40ms ramp rate condition. 

- Giri
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vanlandingham10
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Registered: ‎11-29-2017

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gnarahar
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Registered: ‎07-23-2015

@vanlandingham10  Sorry for the delay on this. 

Since you are using the PS and PL and from what you mention are powering and ramping up at the same time (you sharing rails between PS and PL?) , you will need to follow the TPOR spec. 

TPOR spec begins from the time the last of the monitored supplies (VCCINT,VCCBRAM,VCCAUX) reach 95%. In your case that will be VCCAUX which is 1.8V rail i.e. S2. So TPOR is max 65ms from S2 and PS_POR_B needs to asserted Low for Max of 65ms.  

- Giri
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Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
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vanlandingham10
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Registered: ‎11-29-2017
Thank you for the response. I am ramping the rails (S1, S2, S3) at 2 ms do you mean 15 ms? Isn't the 65 ms for the 40 ms ramp rate?
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gnarahar
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Registered: ‎07-23-2015

@vanlandingham10  Yes its 15ms if you having the 2ms ramp rate with POR override. Since your diagram had ">65ms" notation, I assumed you had the 40ms ramp rate condition. 

- Giri
------------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
------------------------------------------------------------------------------------------------------------------------

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