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bruce_karaffa
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Registered: ‎06-21-2017

Forgive me for asking what is probably a question with an obvious answer somewhere in the 10,000 pages of Zynq documentation but how do you specify the VCCO voltage for a PS bank on a Zynq Ultrascale+.  If I specify an IO standard for a signal on a PL bank, Vivado correctly infers the VCCO for that bank.  How does it work for the PS?  I looked in a ZCU102 project to find a constraints file that specifies the PS VCCOs.  I looked through the board files and couldn't find it.  Yet Vivado knows what voltages are used for the VCCOs.  On my "from scratch" project, it thinks all PS VCCO is 3.3V.  Just ain't right.

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austin
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Registered: ‎02-27-2008

In configuring the MIO from Vivado,

 

In the block diagram, double-clicking on the MPSoC, under MIO, you see banks, with the Vcco voltage choices.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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MIO.bmp
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austin
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1,660 Views
Registered: ‎02-27-2008

In configuring the MIO from Vivado,

 

In the block diagram, double-clicking on the MPSoC, under MIO, you see banks, with the Vcco voltage choices.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

MIO.bmp
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bruce_karaffa
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Registered: ‎06-21-2017

Thanks Austin,  Sorry for the sarcasm but its late on a Friday and I'm trying to work on a board design with lots of new parts (one or two of which may only exist as PDFs, not silicon). 

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