07-19-2018 01:52 AM
RF ADC and DAC latency depends on the configuration of the block.
The DDC in the ADC has a mixer, Decimation and Quadrature modulator correction block as well as a dual clock FIFO for passing data from the tile to the fabric.
The DUC in the DAC has a dual clock FIFO, interpolation, Mixer and a QMC.
Any or all of these can be bypassed.
07-19-2018 07:11 AM
Then I would like to know the latency of the ADC and DAC only, when everything else is bypassed (Decimation, mixer, etc.)
07-20-2018 06:15 AM
I'll have to check on what can be shared.
this is not in the documentation at present.
07-27-2018 07:25 AM
I am interested in ADC and DAC latencies (everything else bypassed) as well. Could you provide us at least an approximate value (plus mines 10 ns)? I would like to buy the kit immediately, but I need the latencies to make a decision - it is not cheap.
Thank you Jiri
11-13-2018 07:20 AM
Still no answer? This is a potential advantage to the RF SOC architecture so I'm surprised Xilinx isn't advertising it. I'd also like to know before I invest the design time for my application.
11-14-2018 01:48 AM
I have done some simulations and for the Zynq UltraScale+ RF Data Converter IP BLock I get the following latencies:
I can't guarantee the correctness of these values, but I think they give you at least an idea.
11-14-2018 02:33 AM
In this case the latency depends on how you have the ADC or DAC set up.
It is not characterised as part of our validation.
As a rough estimate from the digital bench:
ADC datapath latency with all the digital features bypassed would be approximately 190 sample clock
Turn everything in the ADC data path 8x Decimation, mixer etc on and you would see maybe 420 sample clocks.
Similarly for the DAC.
Bypass everything you can expect a latency of approximately 160 sample clocks.
Enable all the DUC functionality, inverse-Sinc etc you can expect to see a latency of perhaps 760 sample clocks.
The numbers are just estimates.
If you want to understand the latency of your set up you should consider running a simulation as Axel has done..
The model is bit and cycle accurate. So you could introduce a step in your input to the ADC or DAC and measure how long it takes to make it’s way through the channel.