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olupj
Explorer
Explorer
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Registered: ‎01-27-2008

RFDC ADC simulation ... issue?

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Hi,

Simulating the RFDC with real input and mixing to Fs/4, -Fs/4.

Here's the config depiction:

olupj_0-1597926568161.png

 

In simulation when I start the real stimulus, Q leads I ( 4 samples / cycle) by 4 cycles. (Not showing start of active stimulus as it's about 335 cycles leading the AXI-S output). You can see where data output goes from static to 4 samples / cycle below.

I haven't analyzed it very much yet but this is a bit surprising.

olupj_1-1597926625384.png

And, just to show how IQ maps to AXI-S:

olupj_2-1597926833069.png

Has anyone experienced something similar? Xilinx - any opinion on what I am seeing here and why?

Thanks, best,

Jerry

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olupj
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Explorer
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Registered: ‎01-27-2008

Hi @pthakare so this might be a data - driven issue.

Resimulated yesterday, I got a 3 (12 sample) AXI-S lead on Q data vs I data.

Simulating today (modified stimulus on analog input), AXI-S I/Q data is aligned.

olupj_0-1598448056092.png

I'll test for that from this point forward (assertions)..

Thanks for the feedback.

Jerry

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pthakare
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Registered: ‎08-08-2017

Hi @olupj 

Are you using example design testbench or your own testbench ?

Example design is generate using 

Configure the IP as per your requirement -> right click and open example design .

The example design detailing is here

https://www.xilinx.com/support/documentation/ip_documentation/usp_rf_data_converter/v2_3/pg269-rf-data-converter.pdf -> Example design section

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olupj
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Registered: ‎01-27-2008

Hi @pthakare 

That's my own testbench derived from the example testbench. I've ripped out the ADC sink to connect other DSP blocks.

As you mentioned it, I took a look at the Xilinx tb AXI-S interfaces and data does start consistently.:

olupj_0-1598367862025.png

However  I configured the system using the same calls in xilinx TB "call_setup_adc_config".

How would you recommend I pursue this? The system in the Xilinx TB and my TB are configured identically.

Thanks,

Jerry

 

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olupj
Explorer
Explorer
558 Views
Registered: ‎01-27-2008

Hi @pthakare so this might be a data - driven issue.

Resimulated yesterday, I got a 3 (12 sample) AXI-S lead on Q data vs I data.

Simulating today (modified stimulus on analog input), AXI-S I/Q data is aligned.

olupj_0-1598448056092.png

I'll test for that from this point forward (assertions)..

Thanks for the feedback.

Jerry

View solution in original post

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olupj
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Explorer
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Registered: ‎01-27-2008

One other aspect that may drive that lag is that, thinking it through, using the coarse mixer the lag of 15 zeros (not 14 necessarily) might be reasonable given a 59 tap filter and using a DSP trick whereas the Q rail only sees the center tap and therefore has a half-filter lag. This doesn't explain the lag I see exactly, however, with FIR2 in the system.

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