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Explorer
Explorer
1,980 Views
Registered: ‎06-19-2014

RFSOC initialization question

My question is about initialization of RF ADC in ZCU111 board.

It is written in pg269 on page 32

"The IP core also handles the configuration and powerup of the data converters. This ensures that the settings specified in the Vivado IDE are applied to the RF-ADCs and RF-DACs immediately after the PL configuration completes."

When I open example design simulation,

1) It first writes simulation speed up registers.

2) write restart state register and restart power on state machine registers for all tiles.

3) Read "restart state registers" and "current state registers" for all tiles until they reach a specific state (powered up).

So these steps are fine as we waited for ADCs and DACs to power up. Then example design write all configuration data to ADCs and DAC tiles like mixer config, mixer mode etc.

My question is: In our custom design, should we just wait for power up (till point 3 above) and start reading ADC values? Or should we program all configuration data too? 

If we follow the text in blue, What I get is, that IP will send all configuration data itself (according to what we programmed in IP config window). If that is true, in example design, where is this data going automatically to IP? All I see is config data is also sent to IP by testbench.

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22 Replies
Explorer
Explorer
1,942 Views
Registered: ‎06-19-2014

Re: RFSOC initialization question

Is there anyone who can answer this query? or aren't there many people at xilinx who can answer queries on these advance devices?

@klumsde : You seem to answer queries on RFSOCs. Will you or someone else?

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Explorer
Explorer
1,916 Views
Registered: ‎06-19-2014

Re: RFSOC initialization question

Is this such a difficult question for people at xilinx to answer? 6 days..no answer

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Moderator
Moderator
1,894 Views
Registered: ‎04-18-2011

Re: RFSOC initialization question

In hardware you get the IP config loaded with the bitfile, there is no need to intervene and change settings unless you need to. 

The Example design has a folder called Imports

In here you will find

demo_tb_axi4l_nano_seq.v

In here you can see it turning off the mixer and turning off Chopping in the ADC since the sim only makes a check that a triangle wave is increasing or decreasing in magnitude and having the mixer on makes no sense because the signal is real and not complex. Chopping won't make an appreciable difference to the output of the ADC and the only thing they will do is add run time. 

If you are doing something more elaborate then you can go in and remove these writes so that you get the IP as is with the mixer enabled etc. 

Keith 

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Explorer
Explorer
1,880 Views
Registered: ‎06-19-2014

Re: RFSOC initialization question

Thanks Keith (@klumsde ) for such a fast reply :S

I got it that in hardware, we dont need to program anything. Just we need to read current status register of ADCs until they are all giving value  "2" ?

In simulation (and hardware), after power up (current state registers giving 2 on reading), do we need to just give data at analog inputs and it will come on AXI channels?

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Moderator
Moderator
1,866 Views
Registered: ‎04-18-2011

Re: RFSOC initialization question

The end state of the tile is 0xF in the startupstartup_fsm.JPG

After this you can consider the output on the ADC AXI stream valid.

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Explorer
Explorer
1,844 Views
Registered: ‎06-19-2014

Re: RFSOC initialization question

I am reading for current state register for value 2 because in example design, When it reads 4 ADC tile current state registers as 2, it takes as configuration completed. 

In custom design, upon your suggestion, I am reading values of current state registers of 4 ADC tiles in 4 registers to reach till value F but design is run for 420 us (in more than an hour) and still it is stuck on value 7 (which is clock configuration step). It is not reaching next state. 

Do I need to run sim for long or am I doing something wrong that it's not moving forward?

Capture.PNG
Capture2.PNG
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Moderator
Moderator
1,778 Views
Registered: ‎04-18-2011

Re: RFSOC initialization question

Hi @a4speaker

I guess at this point I am a little confused about what you are asking. 

A DAC tile in HW can take about 30ms to start and an ADC can take about 40ms. 

In the example design the simulation is sped up using the speedup register and also be doing writes to the Blocks to turn off mixers and some ADC calibration functionality that will not impact a simulation like the example where you are only sampling a ramp and determining if it is rising and falling. 

If I run the simulation again I see that it sets the speedup waits for the tiles to reach an end state of F or B

 

++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
T= 0: Xilinx RF AMS Demo Testbench.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
T= 335100: Delay of 40 cycles requested.
T= 755100: Accelerate SIM startup
T= 855100 D= 855100 (ps): AXI WRITE: AxiAddr=0x00004100, Decode H= 2 L= 64, Data=0x00000001 DCC0_SUPPLY_DETECTION_TIMER_ADDR
T= 975100 D= 120000 (ps): AXI WRITE: AxiAddr=0x00008100, Decode H= 4 L= 64, Data=0x00000001 DCC1_SUPPLY_DETECTION_TIMER_ADDR
xsim: Time (s): cpu = 00:00:19 ; elapsed = 00:00:14 . Memory (MB): peak = 10158.633 ; gain = 0.000 ; free physical = 19026 ; free virtual = 212203
INFO: [USF-XSim-96] XSim completed. Design snapshot 'demo_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:01:01 ; elapsed = 00:01:38 . Memory (MB): peak = 10158.633 ; gain = 0.000 ; free physical = 19026 ; free virtual = 212203
run 500 ms
T= 1095100 D= 120000 (ps): AXI WRITE: AxiAddr=0x0000c100, Decode H= 6 L= 64, Data=0x00000001 DCC2_SUPPLY_DETECTION_TIMER_ADDR
T= 1215100 D= 120000 (ps): AXI WRITE: AxiAddr=0x00010100, Decode H= 8 L= 64, Data=0x00000001 DCC3_SUPPLY_DETECTION_TIMER_ADDR
T= 1335100 D= 120000 (ps): AXI WRITE: AxiAddr=0x00014100, Decode H=10 L= 64, Data=0x00000001 ACC0_SUPPLY_DETECTION_TIMER_ADDR
T= 1455100 D= 120000 (ps): AXI WRITE: AxiAddr=0x00018100, Decode H=12 L= 64, Data=0x00000001 ACC1_SUPPLY_DETECTION_TIMER_ADDR
T= 1575100 D= 120000 (ps): AXI WRITE: AxiAddr=0x0001c100, Decode H=14 L= 64, Data=0x00000001 ACC2_SUPPLY_DETECTION_TIMER_ADDR
T= 1695100 D= 120000 (ps): AXI WRITE: AxiAddr=0x00020100, Decode H=16 L= 64, Data=0x00000001 ACC3_SUPPLY_DETECTION_TIMER_ADDR
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
T= 1715100: Disable the ADC cal to reduce simulation time.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

 

T= 158405100: Wait for data........
T= 163545100: Tile 00 has reached its end state of 0000000f
T= 166125100: Tile 01 has reached its end state of 0000000f
T= 167165100: Tile 05 has reached its end state of 0000000b
T= 167425100: Tile 06 has reached its end state of 0000000b
T= 167685100: Tile 07 has reached its end state of 0000000b
T= 169225100: Tile 04 has reached its end state of 0000000b

 

So you are not using the speedup?

You are not changing at least the ADC cal stuff. 

I don't know why you are surpised that the tile is taking a long time to start in this case. 

Keith 

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Explorer
Explorer
1,769 Views
Registered: ‎06-19-2014

Re: RFSOC initialization question

I am writing 1 to ADC speed up registers (not DAC as I am not using dacs). I am following steps in example design. 

My question is simple. I am waiting for ADC tiles(not DAC tiles) to give value F in current state registers but they are stuck in state 7 and running simulation for hours, they are stuck in state 7 and not changing value. 

Example design sim is also run for a long time but some tiles give value F quite quickly but some tiles are stuck at current state 7. I can't see output on ADC axi channels . 

 

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Moderator
Moderator
1,730 Views
Registered: ‎04-18-2011

Re: RFSOC initialization question

It won't be easy to debug this without me seeing your test bench. 

Can you send me a PM with your email address so I can get you to share the files 

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Explorer
Explorer
1,711 Views
Registered: ‎06-19-2014

Re: RFSOC initialization question

I am not doing much in testbench. Just giving clocks from test bench. I am Sending AXI reads and writes in firmware and not testbench. Here is the sequence of AXI reads writes as copied from example design. (not sending DAC addresses as I am not using DACs).

WRITE : addr: 14100,  data : 1    //sim speed reg ADC tile 0

WRITE : addr: 18100,  data : 1    //sim speed reg ADC tile 1

WRITE : addr: 1C100,  data : 1   //sim speed reg ADC tile 2

WRITE : addr: 20100,  data : 1    // sim speed reg ADC tile 3

WRITE : addr: 14008,  data : b    //ADC tile 0 restart state register

WRITE : addr: 14004,  data : 1    //ADC tile 0 restart power on state machine register

WRITE : addr: 14008,  data : b    //ADC tile 0 restart state register

WRITE : addr: 14004,  data : 1    //ADC tile 0 restart power on state machine register

WRITE : addr: 18008,  data : b    //ADC tile 1 restart state register

WRITE : addr: 18004,  data : 1    //ADC tile 1 restart power on state machine register

WRITE : addr: 18008,  data : b    //ADC tile 1 restart state register

WRITE : addr: 18004,  data : 1    //ADC tile 1 restart power on state machine register

WRITE : addr: 1C008,  data : b    //ADC tile 2 restart state register

WRITE : addr: 1C004,  data : 1    //ADC tile 2 restart power on state machine register

WRITE : addr: 1C008,  data : b    //ADC tile 2 restart state register

WRITE : addr: 1C004,  data : 1    //ADC tile 2 restart power on state machine register

WRITE : addr: 20008,  data : b    //ADC tile 3 restart state register

WRITE : addr: 20004,  data : 1    //ADC tile 3 restart power on state machine register

WRITE : addr: 20008,  data : b    //ADC tile 3 restart state register

WRITE : addr: 20004,  data : 1    //ADC tile 3 restart power on state machine register

Then reading restart state register and current state registers until current state register reads value F

READ  :  addr 14008   // ADC tile 0 restart state register

READ  :  addr 1400C   // ADC tile 0 current state register 

READ  :  addr 18008   // ADC tile 1 restart state register

READ  :  addr 1800C   // ADC tile 1 current state register

READ  :  addr 1C008   // ADC tile 2 restart state register

READ  :  addr 1C00C   // ADC tile 2 current state register

READ  :  addr 20008   // ADC tile 3 restart state register

READ  :  addr 2000C   // ADC tile 3 current state register

 

The current state register value for all ADC tiles is stuck at 7 and not moving forward. Simulation is run for 500 us. 

Do you get now? 




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Moderator
Moderator
1,680 Views
Registered: ‎04-18-2011

Re: RFSOC initialization question

Hi @a4speaker

i've been playing with your simulation and I can reproduce what you see. 

I am not sure why this is occurring. 

I will keep working on this. You don't have to private message me every day for an update. from now we will deal with this via this thread. 

Keith. 

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Explorer
Explorer
1,635 Views
Registered: ‎06-19-2014

Re: RFSOC initialization question

Did this "play" give you any clue or should I wait indefinitely? 

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Explorer
Explorer
1,624 Views
Registered: ‎06-19-2014

Re: RFSOC initialization question

Upon analyzing usp_rf_data_converter_0_por_fsm module, I found out that after some time the status FSM makes pll_error signal high. Can you tell why is this error signal asserted?

Capture.PNG
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Moderator
Moderator
1,619 Views
Registered: ‎04-18-2011

Re: RFSOC initialization question

I am looking at your test bench and design. 

you have the IP set up with the tile PLL enabled and a 250MHz reference clock selected. 

then at the level above in the test bench you have created full rate ADC clocks 

 

always
#0.125 // 4000 mhz clock
begin
adc0_clk_clk_p = ! adc0_clk_clk_p;
adc0_clk_clk_n = ! adc0_clk_clk_n;

adc2_clk_clk_p = ! adc2_clk_clk_p;
adc2_clk_clk_n = ! adc2_clk_clk_n;

end

always
#0.131575 // 3800 mhz clock
begin
adc1_clk_clk_p = ! adc1_clk_clk_p;
adc1_clk_clk_n = ! adc1_clk_clk_n;

adc3_clk_clk_p = ! adc3_clk_clk_p;
adc3_clk_clk_n = ! adc3_clk_clk_n;

end

 

So I am not surprised it is not locking the PLL and you are stuck at step 7

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Moderator
Moderator
1,599 Views
Registered: ‎04-18-2011

Re: RFSOC initialization question

Re-running with a valid input clock, show that it progresses past the clock configuration stage. rfdc_startup_sim.JPG

 

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Explorer
Explorer
1,579 Views
Registered: ‎06-19-2014

Re: RFSOC initialization question

There was confusion reading adc[3:0]_clk_p/n description in table 47 of PG269. It is now understood that if PLL is enabled, we need to give reference clock on pins rather than sampling clock. PLL will generate sampling clock. This solved my issue. 

The final questions on this thread are:

Question 1: restart state registers of ADC are not moving beyond "b" value. Is this the final stage in simulation? (I am asking this as it is written is power up sequence that "done" state is "F"). As you can see in waveform attached, the value of por_sm_state  in rf_data_converter_por_fsm.sv is stable at "14" which is "finish" state. 

Question 2: As you can see in waveform attached, m00_axis_tvalid signal is asserted and data is coming on m00_axis_tdata. Is this valid ADC data? I am asking this as nothing is given on ADC analog input and data is coming on output. Is this some modeled noise?

Capture2.PNG
Capture.PNG
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Moderator
Moderator
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Registered: ‎04-18-2011

Re: RFSOC initialization question

I'll need to look into this question on the tile state question in my mind it should get to 0xF like i see in the hardware.

Unless you tell it to stop at a given state it should go all the way to the end. 

When the ADC tile starts valid should go high and data will start to stream out. I'd imagine the simulation model will have some error built in so for 0 Input you will get 0+some offset at least. 

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Explorer
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Registered: ‎06-19-2014

Re: RFSOC initialization question

@klumsde : I will wait for your reply about done state in simulation. 

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Contributor
Contributor
944 Views
Registered: ‎11-21-2018

Re: RFSOC initialization question

Hi,

It seems that you don't have problems with DAC data,

I don't know why when I use the example design, data simples in stay with indefined values. The test bench creates data samples or I misunderstand? Do you have an idea?

Here a capture of the Vivado simulation.

Capture2.JPG

Do you use Vivado simulator with mixed language? Or something else?

I have also this message : 

[DRC NSTD-1] Unspecified I/O Standard: 127 out of 133 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: irq, s_axi_araddr[23], s_axi_araddr[22], s_axi_araddr[21], s_axi_araddr[20], s_axi_araddr[19], s_axi_araddr[18], s_axi_araddr[17], s_axi_araddr[16], s_axi_araddr[15], s_axi_araddr[14], s_axi_araddr[13], s_axi_araddr[12], s_axi_araddr[11], s_axi_araddr[10]... and (the first 15 of 63 listed).

I change the severity of this message but I think It can give me problems after. Did you have the same?

I hope you will be able to help me, or show me where I can find files to correct this.

Thank you.

Regards,

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Explorer
Explorer
935 Views
Registered: ‎06-19-2014

Re: RFSOC initialization question

I didnt use DAC. If you are running example design, then data should come. one thing I notice is that you are running simulation for around 15 us. ADC and DAC power up takes some time even if you enable simulation speedup registers. Run simulation for around 400 us. It will take long time(on my machine with 16 GB RAM it takes 20 minutes to reach 350 us) to reach 400 us. 

 

Regarding this message, This is related to bit file generation. It says you have not given IO standard to IO signals in xdc file. Vivado needs IO standard for each signal in xdc file.

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Contributor
Contributor
920 Views
Registered: ‎11-21-2018

Re: RFSOC initialization question

Thank you for your answer,

I will try it.

Do you try to use SDK to test converters ? (with this example design)  I want to output rf signal in a spectrum analyser to see real output after generate bitstream but don't really know how to configure data input to the DAC. Do you know where I can find document talking about this? 

Thank you

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Explorer
Explorer
915 Views
Registered: ‎06-19-2014

Re: RFSOC initialization question

Xilinx provides evaluation tool. Read ug1287 on how to input data to DAC.

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