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stefanot
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Registered: ‎06-27-2019

RFSoC ADC input range in simulation

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Dear community,

I am simulating a design with ADCs from the RF data converter. I am injecting the analog (real) signal in the following nodes:
top_tb.u_dut.fpga_top_i.usp_rf_data_converter_0.inst.fpga_top_usp_rf_data_converter_0_0_rf_wrapper_i.rx0_u_adc.VIN_I01_P_real
top_tb.u_dut.fpga_top_i.usp_rf_data_converter_0.inst.fpga_top_usp_rf_data_converter_0_0_rf_wrapper_i.rx0_u_adc.VIN_I01_N_real

I would like to ask
1- if this is the correct point to inject the signal for a simulation;
2- what is the range of the (differential) signal I should use.

I couldn't find this kind on information either in the documentation nor in the example design, so some more insights from experts would be very much appreciated.

Thanks a lot in advance for any valuable help.
Best regards,
Stefano

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klumsde
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Registered: ‎04-18-2011

This is the RF Data converter IP product guide. 

https://www.xilinx.com/support/documentation/ip_documentation/usp_rf_data_converter/v2_4/pg269-rf-data-converter.pdf

I think it needs to get forced on the lowest level of the heirarchy. I would need to check the reason for that. I've a feeling it's more to do with the simulator than anything else. 

Regards, 

Keith 

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klumsde
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Hi @stefanot 

Take a look at this blog. 

https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/RF-Data-Converter-IP-Example-Simulation-Walkthrough/ba-p/1087509

It shows how the forcing works. 

As for the scale. If I remember the sine wave lut we use gets scaled to be inside the 1Vpk-pk differential input range. 

Check the demo_tb_rfadc_tile_source.sv in the example simulation. It should show how we scale the input. 

Keith 

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stefanot
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Registered: ‎06-27-2019

Hi @klumsde,

thanks a lot for the references you have provided.
The problem I am struggling with is that the points where the analog (real) signal is applied (forced) look to be in the encrypted code of the IP and depends from the configuration of the ADC tile(s).
In particular, the piece of code related to this is

always @ (*) begin
   // Map the ADC signals to top level
   adc0_01_p = $bitstoreal(adc_source.vout_00_p);
   adc0_01_n = $bitstoreal(adc_source.vout_00_n);
   adc1_01_p = $bitstoreal(adc_source.vout_10_p);
   adc1_01_n = $bitstoreal(adc_source.vout_10_n);
   adc2_01_p = $bitstoreal(adc_source.vout_20_p);
   adc2_01_n = $bitstoreal(adc_source.vout_20_n);

   // Force the ADC analog input
   force DUT.usp_rf_data_converter_0_ex_i.usp_rf_data_converter_0.inst.rfdc_ex_usp_rf_data_converter_0_0_rf_wrapper_i.rx0_u_adc.SIP_HSADC_INST._vin_i01_p = adc0_01_p; //
   force DUT.usp_rf_data_converter_0_ex_i.usp_rf_data_converter_0.inst.rfdc_ex_usp_rf_data_converter_0_0_rf_wrapper_i.rx0_u_adc.SIP_HSADC_INST._vin_i01_n = adc0_01_n; //
   force DUT.usp_rf_data_converter_0_ex_i.usp_rf_data_converter_0.inst.rfdc_ex_usp_rf_data_converter_0_0_rf_wrapper_i.rx1_u_adc.SIP_HSADC_INST._vin_i01_p = adc1_01_p; //
   force DUT.usp_rf_data_converter_0_ex_i.usp_rf_data_converter_0.inst.rfdc_ex_usp_rf_data_converter_0_0_rf_wrapper_i.rx1_u_adc.SIP_HSADC_INST._vin_i01_n = adc1_01_n; //
   force DUT.usp_rf_data_converter_0_ex_i.usp_rf_data_converter_0.inst.rfdc_ex_usp_rf_data_converter_0_0_rf_wrapper_i.rx2_u_adc.SIP_HSADC_INST._vin_i01_p = adc2_01_p; //
   force DUT.usp_rf_data_converter_0_ex_i.usp_rf_data_converter_0.inst.rfdc_ex_usp_rf_data_converter_0_0_rf_wrapper_i.rx2_u_adc.SIP_HSADC_INST._vin_i01_n = adc2_01_n; //
end

which is in the file demo_tb.v, but it refers to the ADC(s)'s example design, where each tile has one input:

stefanot_0-1618842607383.png

 

In my design I have another configuration and each tile has two (differential) input:

stefanot_1-1618842672299.png

 

so, I am wondering how what is the name of the second input pair.
Is it rx{0,1,2}_u_adc.SIP_HSADC_INST._vin_i23_{p,n}?
How could I check that the signal is applied correctly as these points are within the encrypted IP? Is there any observation point accessible in the encrypted part of the ADC model?

Is there any gain setting that needs to be taken into account? If so, how could I control/observe it in simulation?

Thanks a lot in advance for any further help.
Best regards,
Stefano

 

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klumsde
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Registered: ‎04-18-2011

So for the devices that have dual tiles then the suffix applies like this 

For a dual tile you have VIN01_P/N for the lower channel and VIN23_P/N for the upper channel.

For a quad tile you have the channels numbered 0-3

klumsde_0-1618920192907.png

Is there any gain setting that needs to be taken into account? If so, how could I control/observe it in simulation?

Please let me know what you mean here? there is no gain applied to the input in the ADC tile. 

Regards, 

Keith 

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stefanot
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Registered: ‎06-27-2019

Thanks @klumsde for your feedback.

May I ask you from which document that table-21 comes from?

A related question is that I can see a couple of "real points" (=real ports/signal) in the RF data converter block where the signal can be applied. I have used the ones reported in the example design which sounds more "hidden" points in the encrypted code. I am wondering whether other higher level real ports/signals can also be used to apply the input signal.

Regarding the question about the gain, I was just wondering where the applied signal is somehow amplified inside the ADC before begin actually sampled... but you have already replied.

Thanks again and best regards,
Stefano

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klumsde
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Registered: ‎04-18-2011

This is the RF Data converter IP product guide. 

https://www.xilinx.com/support/documentation/ip_documentation/usp_rf_data_converter/v2_4/pg269-rf-data-converter.pdf

I think it needs to get forced on the lowest level of the heirarchy. I would need to check the reason for that. I've a feeling it's more to do with the simulator than anything else. 

Regards, 

Keith 

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stefanot
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Registered: ‎06-27-2019

Thanks a lot @klumsde for your feedbacks.

I will accept the previous reply as solution so that we can consider this thread closed.

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klumsde
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Registered: ‎04-18-2011

OK. 

A quick check with the IP folks suggests that the force needs to happen at this kind of low level of the heirarchy. 

We also updated the point at which we force the signal a while back. It’s now at SIP_HSADC_INST.VIN_I01_P rather than at SIP_HSADC_INST._vin_i01_p.

I think the force has to be in the SIP_HSADC_INST module though.

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