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Observer michaelellis
Observer
533 Views
Registered: ‎03-27-2019

RFSoC Example Design - ADC Source

I have created the RFSoC example design and have a question about the ADC source block.  The simulation waveforms created by this block appear to be 4x slower than the debug statements and the simulation code indicate.  The signal for slice 0 of each tile is supposed to be a 15.625 MHz sine wave but the simulator waveform shows a 3.90625 MHz sine wave.  Similarly, the signal for slices 1, 2, and 3 should be 31.25, 62.5 and 125 MHz but the simulator shows 7.8125, 15.625 and 31.25 MHz, respectively.  The ADC configuration indicates 4x decimation.  Does this imply that the external data source for this example design must be pre-decimated by 4x in order to function properly?

 

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Moderator
Moderator
477 Views
Registered: ‎04-18-2011

Re: RFSoC Example Design - ADC Source

Which version of vivado is this seen on? 

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Observer michaelellis
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Registered: ‎03-27-2019

Re: RFSoC Example Design - ADC Source

Version 2019.1

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Moderator
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441 Views
Registered: ‎04-18-2011

Re: RFSoC Example Design - ADC Source

hi @michaelellis 

This sounds familiar. I need to look back on my notes. 

Let me double check it and get back to you.. 

 

Keith 

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Observer michaelellis
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Registered: ‎03-27-2019

Re: RFSoC Example Design - ADC Source

Is there any update on this issue?

 

Regards.

Michael

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Observer michaelellis
Observer
362 Views
Registered: ‎03-27-2019

Re: RFSoC Example Design - ADC Source

@klumsde - Just checking in once more to see if there is any new information on this topic.

 

Michael

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Moderator
Moderator
342 Views
Registered: ‎04-18-2011

Re: RFSoC Example Design - ADC Source

Hi @michaelellis 

Sorry for the delay. I think the comments are wrong and there is a decimation added incorrectly. 

We are still looking into this a bit. 

I will update you in the next day or two. 

 

Keith 

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Observer michaelellis
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Registered: ‎03-27-2019

Re: RFSoC Example Design - ADC Source

@klumsde - Just one more check before heading into the weekend. Any progress?
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Moderator
Moderator
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Registered: ‎04-18-2011

Re: RFSoC Example Design - ADC Source

Hi @michaelellis

It looks like the comment and the frequency setting going into the fft frequency checker are both multiplied by the decimation setting.

This is not correct. 

We will aim to fix it in 2019.2

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