08-15-2019 08:06 AM
I have created the RFSoC example design and have a question about the ADC source block. The simulation waveforms created by this block appear to be 4x slower than the debug statements and the simulation code indicate. The signal for slice 0 of each tile is supposed to be a 15.625 MHz sine wave but the simulator waveform shows a 3.90625 MHz sine wave. Similarly, the signal for slices 1, 2, and 3 should be 31.25, 62.5 and 125 MHz but the simulator shows 7.8125, 15.625 and 31.25 MHz, respectively. The ADC configuration indicates 4x decimation. Does this imply that the external data source for this example design must be pre-decimated by 4x in order to function properly?
08-18-2019 01:42 PM
Which version of vivado is this seen on?
08-20-2019 02:31 AM
This sounds familiar. I need to look back on my notes.
Let me double check it and get back to you..
09-03-2019 08:22 AM - edited 09-03-2019 08:29 AM
09-03-2019 09:42 AM
Sorry for the delay. I think the comments are wrong and there is a decimation added incorrectly.
We are still looking into this a bit.
I will update you in the next day or two.
09-06-2019 01:54 PM
It looks like the comment and the frequency setting going into the fft frequency checker are both multiplied by the decimation setting.
This is not correct.
We will aim to fix it in 2019.2