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yfuji38
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Registered: ‎11-13-2017

RFSoC RF DAC data stream format

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Hi,
I started using RFSoC device on ZCU111 board. First, I am trying to generate signals using RF DACs. The DACs are configured for a simple mode:
- Real output
- x1 interpolation
- 16 samples per AXI4-stream cycle
- Mixer bypassed
- 256 bits data width

I succeeded in feeding data to the DACs, but could not find information on data format of the AXI4-stream in the product guide PG269 (Zynq UltraScale+ RFSoC RF Data Converter 2.0).

Looking at actual output waveform, it seems like:
- AXI4-stream data has 16 bits boundaries
- The lowest data (tdata[15:0]) is transmitted first.
- Every 16 bits data is signed integer format. (min 0x8000 ... max 0x7FFF)
- In the 16 bits data, the lowest bit 0 and 1 are not used.

Is this assumption correct?

Thank you,

 

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klumsde
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Registered: ‎04-18-2011

This detail is actually in the product guide.

 

figure 58 shows the arrangement of the samples in the axi stream

tdata 15:0 is sample 0 and this is transmitted first 

 

Table 52 shows the 16 bit 2's compliment data word format.

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14 Replies
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Registered: ‎09-12-2018

Hi,

 

You need to drive the DAC with an AXI Streaming interface. You can look up the details pg085 AXI4 Stream Infrastructure.

 

I got a similar problem. I got ZCU111 eval board. I simply wants to drive the DAC from PL logic, e.g., a pure sine wave from the DDS IP. Do I still need the PS and run a bare metal application? Or there is a way to do this without touching the PS and SDK?

 

Thanks.

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klumsde
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Registered: ‎04-18-2011

This detail is actually in the product guide.

 

figure 58 shows the arrangement of the samples in the axi stream

tdata 15:0 is sample 0 and this is transmitted first 

 

Table 52 shows the 16 bit 2's compliment data word format.

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yfuji38
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Registered: ‎11-13-2017

Hi,

In my case, feeding data from BRAM in PL logic to the DAC core.
It was a little complicated. But I had to created a bare metal application to initialize the RF DACs and on-the-board clock ICs. Then the AXI4-Stream started running.
An issue is that data format in the AXI4-Stream is not clear.

 

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yfuji38
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Registered: ‎11-13-2017

Hi @klumsde,

Thank you for your reply.
Now the data format is clear to me.

Looking at figure 58 (attached), it shows data for sample 15..0 is included in the first 256-bits data. It is okay. But I could not see alignment of 16 samples data in the 256-bits.

I hope the information is included in the product guide.

 

Thank you.

 

Screenshot from 2018-10-04 09-37-50.png

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chyrie19
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Registered: ‎11-21-2018

Hi,

Do you use AXI4-stream interconnect between BRAM and usp_rf_data_ converter?  @yfuji38 

Do you solve the issue with AXI4-stream data format?

Is it possible for you to post a screen shot with the architecture Vivado?

 

Thank you

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yfuji38
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Registered: ‎11-13-2017

Hi,
I am not using AXI4-stream interconnect, but created a waveform generator module which is written in RTL. Just FYI, see attached block diagram. It is for testing the RF DACs. I checked that the actual output waveform was good.
Hope this helps.

Screenshot.png
nicolas05
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Registered: ‎06-05-2019

Helo @yfuji38 ,

 

I am also trying to drive the DACs using data (binary random sequence) loaded in the memory in the board. What IP architecture can I use to generate the analog waveform in the DAC outout? I know I have to use the RF data converter, but I do not find how can I "feed" it with the digital data.

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yfuji38
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Registered: ‎11-13-2017

Hi @nicolas05,

I created wfm_gen module which feeds data to the DAC. The module includes dual port RAM IPs for each DAC channel. The address to the RAM is incremented repeatedly. Those parts are written in Verilog RTL.

If you use PL DDR4 memory on the board, you might have to use MIG (DDR4 memory interface) IP and AXI stream generator, etc.

nicolas05
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Registered: ‎06-05-2019

Hi @yfuji38 ,

Thanks for the answer. It looks simpler for me to use the AXI traffic generator for driving the DAC. Also, the traffic generator IP is driven by a Zynq uP, right? If I understand correctly, one has to use a Baremetal library inside it. I am still searching on how to achieve that.

 

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yfuji38
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Registered: ‎11-13-2017

Hi @nicolas05,

The AXI traffic generator can be used for generating AXI stream data. But it looks like the IP is for testing the AXI modules/interconnections. The traffic pattern is limited.

If you would like to generate data pattern by using AXI mapped memory, the AXI DMA Controller or the AXI Datamover could be usable.

https://www.xilinx.com/products/intellectual-property/axi_dma.html

https://www.xilinx.com/products/intellectual-property/axi_datamover.html

 

nicolas05
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Thank you!
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kinmand
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Registered: ‎06-27-2019

The digital data format is in PG269 (v2.1) December 5, 2018, Zynq UltraScale+ RFSoC RF Data Converter.

 

I created my own custom IP that I can program waveform vectors generated in Octave. Mybe this will work for you?

 

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kinmand
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Registered: ‎06-27-2019

Forgot to mention table 57 on p. 156 for the data format. You already have the sample position format.

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nicolas05
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Registered: ‎06-05-2019

Hello @kinmand ,

Sure that would be of great help! From what I understand, I should 

-generate data using Octave/matlab

-load it in memory on board

-access the memory via DMA and stream it in AXIS packages

-get that packages to de DAC via RFDC IP

Thanks a lot!

 

 

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