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1,134 Views
Registered: ‎07-18-2019

RfSoc ZCU111 DAC implementation with Baremetal

Hello,

I have been trying to implement a DAC example in order to generate a sine waveform on DAC output.

The block diagram of my design is the following,BlockDiagram.png

The usp_rf_data_converter was set as following:img1.pngimg2.pngimg3.png

The dds_compiler block is responsible for generating the sine waveform. I think that it correctly generates the sine waveform, since I am able to obtain the exepected signal and see it on ILA. However, when I connect an oscilloscope to usp_rf_data_converter I only see a constant voltage instead of a sine wave. DDS_compiler block was set as following:

img4.pngimg5.pngimg6.pngimg7.pngimg8.png

I was not able to attache the project's code on vivado 2019.1 because it is larger than the maximum allowed, although I can send by e-mail if anyone wants to try it. I attached the sdk main. I used the baremetal library.

If anyone has insight on this problem it would be greatly appreciated.

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Registered: ‎11-10-2017

Hi @marianaferreiraramos ,

Wanted to know if you got your this issue resolved ?? I am too facing a similar issue. When I try to execute the read_write example present in github (link:  https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/rfdc/examples/xrfdc_read_write_example.c) it executes fine, but I do not see any wave or output in my oscilloscope. Please let me know if you got this resolved and how.

Thanks,

V

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1,085 Views
Registered: ‎04-04-2019

I wouldn't mind taking a look at it. User name is email.

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1,074 Views
Registered: ‎07-18-2019

Hi chris@cleverpacket.org ,

I just sent an email with the code. Thank you.

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1,014 Views
Registered: ‎07-18-2019

Hi @vish.bh30 ,

I couldn't solve the issue yet. My code is in the following link: 

https://uapt33090-my.sharepoint.com/:f:/g/personal/marianaferreiraramos_ua_pt/Eq7cSZNwvmdLqxabanS1RYYBvI0hV9OYlTZdM4jhxlxAhw?e=OnY9Of

Please check if you can execute it. With this sdk I am only able to see a constant output voltage instead of a sine wave, as you can see on ILA input.

If you have made any progress please let me know.

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Registered: ‎11-10-2017

Hey @marianaferreiraramos ,

I tried using your project files as you shared as well as I also tried following the steps as discussed in this thread : https://forums.xilinx.com/t5/UltraScale-Architecture/RfSoc-ZCU111-DAC-implementation-with-Baremetal/m-p/1007906

 

The issue what i am getting now is , while I am able to see the jump in the voltage, I am still not able to get the waveform on oscilloscope as you mentioned in the above mentioned thread. I tried modifying the DDS_compiler to have Taylor Noise filter, and the solution discussed in the thread but it's not working. Can you please share the step by step details of what you did there to get the sine waveform ? 

 

 

EDIT : I am able to get information in the COM terminal as I figured there was a problem with the code of trying to check for tile 0, while I was using 1 in the hardware design. But still stuck with the issue of sine waveform.

 

Also this is what I am still getting in the COM terminal:

Teraterm_XSDK.PNG

 

Image :

Voltage changeVoltage change

No FreqNo Freq

Please let me know what needs to be corrected or what other changes you made to get the waveform ?

 

Thanks ,

Vish

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Registered: ‎07-18-2019

@vish.bh30 I already updated the files in the folder I shared.

I believe that your problem is also the clocks. Check if the clocks you have in your design are the same in the SDK. I shared a example.c file in https://forums.xilinx.com/t5/UltraScale-Architecture/RfSoc-ZCU111-DAC-implementation-with-Baremetal/m-p/1021820#M11910 that works for LMX 245.76MHz. If you want to use another clock you have to change the table of LMK in the example.c file and choose the correct frequency for LMX. In any way, these clocks must match the clocks in the design. The Taylor filter is only to correct the signal, because I think that DDS generates a truncated sin and should have this filter. But when I needed to use that I was able to see in the oscilloscope a non-constant signal. So, try to use the example.c and check the clocks agree.

If you need anything or it does not work let me know.

 

Mariana

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Registered: ‎11-10-2017

@marianaferreiraramos 

 

Hey thanks for the reply. I will check the example.c file on Monday and see if things work ok or not. I used your project as it is as i mentioned. Also i tried modifying the clocks as 400, check the below images but i got nothing on the Vivado simulation also. I will check further on Monday as well. Please let me know if you get something out of my observations.

 

Block DesignBlock Design

DDS Compiler ModifiedDDS Compiler ModifiedRF DATA CONVERTER MODIFIEDRF DATA CONVERTER MODIFIEDSIM_1SIM_1

SIM Full ViewSIM Full View

Thanks again,

Vishal

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Registered: ‎07-18-2019

Hi @vish.bh30 ,

 

I updated the files in the folder https://uapt33090-my.sharepoint.com/:f:/g/personal/marianaferreiraramos_ua_pt/EpmkYweDKdpPvlG5w8dmG_4BthkakbQFeSfS8pi0JM272A?e=GZA2gh .

I saw in your pictures that you have the ILA, but you should delete it or put a broadcaster before it. Otherwise, it will not work according with the moderators. Nevertheless, I replaced the 400MHz frequency in order to match the 245.76MHz I used in the PLL clocks configuration, as you can see in the picture bellow:

Untitled.png

Mariana

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Registered: ‎07-18-2019

@vish.bh30  these are my clock signals:

 

Untitled.png
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Registered: ‎02-18-2020

Hi,

I am trying to replicate the circuit as you have done but am not getting the sine wave. Also do I need to write a test bench code for the same or is it sufficient if we force value to the inputs ?

Hope to get a reply back soon.

 

Thanks,

Pournima

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