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marianaferreiraramos
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RfSoc ZCU111 DAC implementation with Baremetal

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Hello,

I have been trying to implement a DAC example in order to generate a sine waveform on DAC output.

The block diagram of my design is the following,

BlockDiagram.png

The usp_rf_data_converter was set as following:img1.png

 

img2.png

 

img3.png

The dds_compiler block is responsible for generating the sine waveform. I think that it correctly generates the sine waveform, since I am able to obtain the exepected signal and see it on ILA. However, when I connect an oscilloscope to usp_rf_data_converter I only see a constant voltage instead of a sine wave. DDS_compiler block was set as following:img4.png

 

img5.png

 

img6.png

 

img7.png

 

img8.png

 I used the baremetal library.

Project's code is in the following link: https://uapt33090-my.sharepoint.com/:f:/g/personal/marianaferreiraramos_ua_pt/Eq7cSZNwvmdLqxabanS1RYYBvI0hV9OYlTZdM4jhxlxAhw?e=OnY9Of.

If anyone has insight on this problem it would be greatly appreciated.

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klumsde
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I would cut out the clock programming from the SW application.

I would make the pay close attention to the tile set up, you are setting the reference clock to 122.88 depsite the fact that it is not reccommended. 

Make it 245.76MHz here.  

Also you have the axi stream clock clocked by the tile output clock which is 245.76, the requirement here is 491.52

So you need to make the clk_dac0 equal to 491.52. 

Also you seem to try to connect this signal to dac0_clk which is the incoming tile clock, this is wrong. the dac0_clk should be external. then the output clock from the tile can be used in your fabric. 

Program the clock with the system controller GUI. make all the LMX output the 245.76Mhz reference clock as shown earlier. 

 

 

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klumsde
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Hi @marianaferreiraramos 

In this case the first step I would do, if you haven't done it already is to boot the RF Analyzer Bitstream or the TRD for ZCU111, then try output this sine wave from the DAC you mention. If that works you know the hardware set up is good. 

Next I would use the PS to check the status of the IP. In particular the start up state machine that is part of the IP. If this is at it's end state the tile is running. Then we know the issue is somewhere before the DAC streaming input. I am guessing you see something coming out of the Streaming output you have connected to the ILA?

In this case as well, I don't think you can just connect the streaming data to 2 different IPs you need to put in the broadcaster to drive the ILA and the RFDC, if I remember correctly. Try this step as well.  

If the tile is not at it's end state you should be able to tell what is wrong by the state it is in. Usually the problem comes becuase you don't have the tile input clock running, so the state machine fails at the sample clock detect stage. 

In this case I would remind you that you have to program the clocks from the RF PLLs on the ZCU111. The way to do this is via the SW, there are 2 examples in the driver source on how to do this. Alternatively you could use the system controller to do this. 

Try the suggestions here and let us know how you get on. 

 

Keith 

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zhendon
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Hi

Keith answered everything you can try on at the moment.

My two cents here is the clock needs to be programed if you start the board with JTAG. You can have a quick check on board of the clock leds. There are four leds on the left hand side of the board. It should stay on green after programming.

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marianaferreiraramos
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Hi @klumsde ,

I tried to boot the RF Analyzer Bitstream, but I have a recurring error. I will detail the steps so you can help me what I am doing wrong please.

First I programmed the clocks using the system controller:

 

sc.png

 

board.png

The four leds are green.

After, I chose one of the bitstream and boot the board. But I always got an error in power-on state machine (7)

error.png

I also attach the following picture,

error2.png

 

Hope you can help me.

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zhendon
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Hi @marianaferreiraramos 

It seems that the RFSoC failed to start up due to the clock issue.

I am curious about your RFSOC IP settings. From the previous posts I can see the internal PLL is bypassed.

But by according your current clock configuration, it needs you to enable ADC/DAC internal PLLs and set the input adc/dac clock at frequency 122.88Mhz.

thanks,

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klumsde
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Are you loading the prebuilt ZU28DR bitstream that comes with the Analyzer?

If so you need to set up the RF Plls to provide 245.76Mhz clocks that feed the tile PLLs.scui_rfpll_forum.JPG

If you create the analyzer design from your IP then you need to program the RF PLLs accordingly.For this you will need to create the programming files in the TicsPro tool from TI

 

 

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marianaferreiraramos
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Hi @klumsde and @zhendon,

with your suggestions I was able to boot the RF analyzer and got a sine wave in the oscilloscope. Now, I want to try to see the same sine waveform but using my design. I already changed the DAC clock reference in the hardware. Now I will move to the step that @klumsde  suggested to use the PS to test the IP status. Where can I find it?

 

Thanks a lot for your help.

Mariana

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klumsde
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You need to create the SDK project and boot the design.

You need to do something like this in the baremetal application

Status = XRFdc_GetIPStatus(RFdcInstPtr, &myIPStatus);
if (Status != XRFDC_SUCCESS) {
return XRFDC_FAILURE;
}

Then check on the tile status

It gets the status of every tile so you can just do 

DACTileStatus[0/1/2/3] like below

int powerup_status;
int tile_state;

powerup_status = myIPStatus.DACTileStatus[0].PowerUpState;
tile_state = myIPStatus.DACTileStatus[0].TileState;

printf("DAC PowerUp Status: %u\n", powerup_status);
printf("DAC Tile State: %u\n", tile_state);

I'd also take a look at that ILA connection to. Put in a broadcaster to go to 2 places.

Keith 

 

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klumsde
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Hi @marianaferreiraramos

Amy update here?

 

Keith

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marianaferreiraramos
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Hello @klumsde ,

I have been trying to implement that, but I think I may have any error in clock. This is my block diagram with clock signals:

block diagram.png

This is the usp module system clocking:

usp.png

Furthermore, I attached the sdk main code here, and I got this on terminal:


Configuring the Clock
LMK04208 configuration write done
LMX configured to frequency 2457600
I2c1 I2CTOSPI LMX2594 PLL configuration done
Starting PS!

Getting state!

DAC PowerUp Status: 0
DAC Tile State: 7
metal: error: Requested block not available in XRFdc_GetBlockStatus.

What should I do?

 

Thanks,

Mariana

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marianaferreiraramos
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@klumsdesorry, I was using dac 1 intead of 0, as I sent before.

So, I changed the code

powerup_status = myIPStatus.DACTileStatus[1].PowerUpState;
tile_state = myIPStatus.DACTileStatus[1].TileState;

And I got the following output:

Hello RFDC!

Configuring the Clock
LMK04208 configuration write done
LMX configured to frequency 2457600
I2c1 I2CTOSPI LMX2594 PLL configuration done
Starting PS!

Getting state!

DAC PowerUp Status: 16384
DAC Tile State: 0
metal: error: Requested block not available in XRFdc_GetBlockStatus

And the value at DAC output is a constant voltage instead of a sinewave.

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klumsde
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I would cut out the clock programming from the SW application.

I would make the pay close attention to the tile set up, you are setting the reference clock to 122.88 depsite the fact that it is not reccommended. 

Make it 245.76MHz here.  

Also you have the axi stream clock clocked by the tile output clock which is 245.76, the requirement here is 491.52

So you need to make the clk_dac0 equal to 491.52. 

Also you seem to try to connect this signal to dac0_clk which is the incoming tile clock, this is wrong. the dac0_clk should be external. then the output clock from the tile can be used in your fabric. 

Program the clock with the system controller GUI. make all the LMX output the 245.76Mhz reference clock as shown earlier. 

 

 

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marianaferreiraramos
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@klumsde, Where can I find the txt file for 245.76Mhz?

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klumsde
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Hi @marianaferreiraramos 

The SCUI comes with some of these clock files pre installed. 

It looks for them along this path hereforum_clkfiles.JPG

In the GUI itself entering LMK04208.txt for the jitter cleaner and LMX2594_245M76.txt in each of the 3 PLL fields will work. 

As you program them you should see the 4 leds on the right hand side of the board illuminate. rfpll_leds.jpg

 

 

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marianaferreiraramos
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@klumsde  I made the download of the two versions 2018.3 and 2019.1 and in both I have only these files:

scui.png

In any of them I have the file LMX2594_245M76.txt.

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klumsde
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My apologies. 

Use the files attached. 

 

 

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marianaferreiraramos
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No problem @klumsde .

I did what you suggested.

I got the following,

Hello RFDC!

Starting PS!

Getting state!

DAC PowerUp Status: 3214499984
DAC Tile State: 2167440650
DAC Sampling Frequency: 3.932

DAC00 Status
AnalogDataPathStatus - 16
DigitalDataPathStatus - 129
DataPathClockStatus - 1
IsFIFOFlagsEnabled - 3
IsFIFOFlagsAsserted - 0

And I already have a signal. But it is not a sinewave. However we are closer.

The signal I got is the following:

thumbnail_IMG_20190827_153529.jpg

But maybe here the problem is on the DDS_compiler. What do you think?

Thanks for you help.

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klumsde
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Yes potentially the dds compiler I think since the analyzer bitstream doesn't give this result.

How does it look if you change the output from the dds to something else? 

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marianaferreiraramos
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Hello @klumsde ,

I added a Taylor series corrected in noise shapping and the problem is solved.

Thank you for your help :)

nvenugop
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@marianaferreiraramos Greetings!

I tried the same project with the files attached in this thread.
I am quite successful in getting a constant output from the DAC ( DAC228_T0_CH1).

However, I am not able to generate a sine wave as mentioned.
Could you pls help us with the more details on this part? Is there any specific settings that needs to be configured from the 
zcu111_scui ?


Thanks in advance.


Nanda

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vish.bh30
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@klumsde  @marianaferreiraramos  @zhendon 

 

Could anyone please take a look at my response on the follwing thread : https://forums.xilinx.com/t5/Evaluation-Boards/RfSoc-ZCU111-DAC-implementation-with-Baremetal/m-p/1007304#M23714

I followed what was mentioned here, but still not able to get any sine waveform.

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marianaferreiraramos
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Hi @nvenugop,

I realized that the main problem is related with the clocks. You have to check in your design if the clocks of the PLL are the same as the clocks you program in scui or using software. If you chose to program the clocks using the baremetal application, the table of LMK04208 should be changed according the clock you need. You can use the SCUI and the txt files attached, or the sdk project that I also attached in this comment.

Try to check my solution and if you have any more doubts pls let me know and I'll try to help you with that. With this SDK you don't have the need to use the SCUI separetly. It already works. But make sure the clocks in you design match the clocks I chose.

The project folder has a size that is not allowed to attach. I attached the main files but if you need more than them let me know and I arrange another way to share the project with u.

 

Mariana

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marianaferreiraramos
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@nvenugop  sorry, I forgot attached the txt files for the SCUI.

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marianaferreiraramos
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@vish.bh30  I will take a look on this.

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nvenugop
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Hi @marianaferreiraramos 
Thank you for the help, We were able to generate the sinewaves. The DAC output is generating 10Mhz sine waves. Any suggestion on how to change the frequency of the generated waves?. Additionally, I am trying to read the DAC output in ADC part.( DAC to ADC loop back), however when I enable the ADC in the board design, the clock for ADC is missing and I tried running connection automation. When I do that, the DAC is not producing sine waves but just a high voltage constant signal. Any suggestions on this?

Thanks in advance.

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marianaferreiraramos
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Hi @nvenugop ,

the frequency of the generated waveforms can be changed on the DDS compiler block. You have to change the phase increment. For more details you have the IP documentation: DDS_compiler_doc . I did these simple calculations to easily find the correct increment:

clear all;
close all;
clc

f_out = 10*10^6; % Hz
f_clock = 491.56*10^6; %Hz
f_resolution = 1; %Hz
phase_width = ceil(log2(f_clock/f_resolution)); % decimal


phase_inc = (f_out*(2^(phase_width)))/f_clock;
ff = (f_clock*phase_inc)/(2^phase_width);

phase_inc_bin = dec2bin(phase_inc,phase_width)

Regarding to the ADC, I did not try it already. However, I think that a read somewhere that maybe you should pay attention to sysref signal, because I think that it is that signal that is responsible for syncronizing all DAC and ADC. First, I am trying to deal with theamplitude range of the DAC.

 

 

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vish.bh30
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Hello @marianaferreiraramos ,

Thanks for sharing the information. The design that you shared with me for 491.52MHz works fine with 245760 frequency.

Based on the calculation u gave i tried modifying it to 1000MHz :

f_out = 999*10^6; % Hz
f_clock = 1000*10^6; %Hz
f_resolution = 1; %Hz
phase_width = ceil(log2(f_clock/f_resolution)); % decimal

phase_inc = (f_out*(2^(phase_width)))/f_clock;
ff = (f_clock*phase_inc)/(2^phase_width);

phase_inc_bin = dec2bin(phase_inc,phase_width)

 

I got the following output:

f_clock = 1.000000000000000e+09,
f_out = 999000000,
f_resolution = 1,
ff = 999000000,
phase_inc = 1.072668082176000e+09,
phase_inc_bin = '111111111011111001110110110010',
phase_width = 30

 

When i updated this in the Vivado for DDS and RFDC, i am not getting any signal output. 

I tried updating the LMK4208 clock config array also to this: 

unsigned int LMK04208_CKin[1][26] = {
{ 0x00160040,0x80140320,0x80140321,0x80140322,
0xC0140023,0x40140024,0x80141E05,0x03300006,
0x01300007,0x06010008,0x55555549,0x9102410A,
0x0401100B,0x1B0C006C,0x2302886D,0x0200000E,
0x8000800F,0xC1550410,0x00000058,0x02C9C419,
0x8FA8001A,0x10001E1B,0x0020F45C,0x0180033D,
0x0200033E,0x003F001F }};

Please let me know if this is correct . My guess is the config array is not correct. Please let me know what values work for 999MHz output frequency. I am also curious to know how you set the LMK4208 register values for LMK04208_CKin[1][26] 

 

Please find the Vivado snapshots attached

 

DDS_999_0_0.JPGDDS_999_0_1.JPGDDS_999_0_2.JPGRFDC_999_0.JPGRFDC_999_1.JPG

 

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jorgitog1
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I have seen this block diagram in more than one post.  Is this an example block diagram? If so, could you please tell me how to access it?

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