Source synchronous clocking

[apogeedbkxilinx]

I'm interested in the recommendations/restrictions for implementing source synchronous clocked in the Kintex Ultrascale.  Looking in the SelectIO and Clocking user guides I did not see any explicit rules.  The closest I found was in the Clocking Resources User Guide (UG572) which states "Byte lane clock (DBC and QBC) input pin pairs are dedicated clock inputs directly driving source synchronous clocks to the bit slices in the I/O banks."

In particular I'm concerned about pin assignment restrictions on the pin used to drive the clock input and how many Byte Lanes or Banks of input data that clock can drive in a source synchronous input architecture.

I'd like similar information on source synchronous output clocking/data as well.

Thanks.

[bisector · Accepted solution]

Another snippet of information: http://www.xilinx.com/support/answers/64117.html

The High Speed SelectIO wizard in Vivado might be your safest bet. Found some interesting clock restrictions there.

http://www.xilinx.com/support/documentation/ip_documentation/high_speed_selectio_wiz/v1_1/pg188-high-speed-selectio-wiz.pdf