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Participant
Participant
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Registered: ‎04-08-2015

Supply Voltage

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I am doing a design with the ZYNQ Ultra-Scale.

While I am using a lot of the FPGA, I am not using many I/O

The analog part of my design is all 3.3V which I want to connect to bank 26

The banks 64-66 are all limited to 1.8V... I do not need them.

Do I still have to connect 1.8V to these banks to avoid latchup or can I ignore them?

The documentation is rather specific about the power sequencing...

 

Thanks

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Contributor
Contributor
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Registered: ‎09-14-2017

During the schematic design XTP427 "Ultrascale plus schematic review checklist" Excel document is very useful reference. It has instructions also for this case.

 

VCCO of unused I/O banksFor maximum ESD protection in an unused bank, all VCCO and I/O pins in that bank should be connected together to the same potential, whether that be ground, a valid VCCO voltage, or a floating plane. If you plan on migration, connect the unbonded I/O banks to the appropriate VCCO supplies. Make sure the voltage limits are followed for the HD and HP I/O's.

 

--Kim

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Contributor
Contributor
1,270 Views
Registered: ‎09-14-2017

During the schematic design XTP427 "Ultrascale plus schematic review checklist" Excel document is very useful reference. It has instructions also for this case.

 

VCCO of unused I/O banksFor maximum ESD protection in an unused bank, all VCCO and I/O pins in that bank should be connected together to the same potential, whether that be ground, a valid VCCO voltage, or a floating plane. If you plan on migration, connect the unbonded I/O banks to the appropriate VCCO supplies. Make sure the voltage limits are followed for the HD and HP I/O's.

 

--Kim

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Participant
Participant
1,212 Views
Registered: ‎04-08-2015

Kenkovaa

 

You are saying, that I can connect the unused bank (in my case the bank which is limited to 1.8V) simply to ground (0V)

this is connecting VCCO and all I/O pins to ground and NOTHING bad will happen ?

Hope you are right, because this is difficult to change once the PCB is done.

I wanted an answer from a Xilinx Engineer to make sure, but nothing.

 

You maybe correct, because the power up sequence states that the VCCO voltages are the last ones to be applied.

Then for a very brief moment the VCCO is actually zero

Alternatively I could add a 1.8V PS which does nothing.

 

AJS

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Moderator
Moderator
1,178 Views
Registered: ‎07-23-2015

@annosauer1 The document @kenkovaa quoted his response from is a Xilinx document :) 

Do also use UG583 while designing your board. UG583 defines the below for Unused Banks (Unconnected VCCO) which is similar to the one mentioned in XTP427 quoted above

 

vcco_unconnected.JPG

 

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Participant
Participant
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Registered: ‎04-08-2015

Neither UG583, DS925 or UG1085 (TRM) say specifically

but I think for the JTAG to work, the PL (1.85V) needs to be present.

This means I have to supply all power rails, even when I only use Bank26 and the MIO.

 

AJS

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