03-15-2016 07:57 AM
it seems that in 2015.4.1 Displayport IP core has major problem causing the GTREF clock to be unroutable, there are answer records that indicate that similar problems existed, and have been solved, but it seems that in the case of Displayport there is still as showstopper bug in 2015.4.1
or is there some trick or patch to get the clock rouiting to pass DRC ?
03-16-2016 12:25 AM
03-16-2016 02:05 AM
03-21-2016 05:27 AM
03-21-2016 06:13 AM
I tested this locally with the same XCI file and the device name and do not see any such routing issues. I did this with the example design using IP Catalog and not in the IP Integrator. In any case this should not be an issues.
Please try with the example design at your end and let me know if you see failures. This was tested with 2015.4.1
03-21-2016 12:11 PM
well we need the IPI flow, I can try the IP catalog to see if has routing problems
I am currently trying to back-port the DisplayPort 7.0 from Vivado 2016.1 to Vivado 2015.4, well this does not to be a good idea either.. :(
03-21-2016 10:53 PM
2016.1 is not yet released. How do you have access to this version of the tool?
03-24-2016 01:56 AM
I have tested again on 2015.4 also, the problem was in our design, I had connected an on-chip frequency counter IP core to lnk_clk_ibufds_out pin !! This is a no-go of course, it caused unroutable error that looked like it is on the INPUT path but the problem was in the clock consumer. The link clock can only be used in general fabric using lnk_clk output in ultrascale+
I think fpr 7 series would the second direct output also have path to PL, well with ultrascale its different.