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gsmecher
Explorer
Explorer
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Registered: ‎01-21-2011

UltraScale native mode I/O at lower clock rates

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UG571 describes "component mode" and "native mode" I/Os:

  • "Component mode" provides a friendly backwards compatibility layer (I'm familiar with 7-series devices, so this is helpful), but
  • "Native mode" is a closer match to what's actually present on the silicon.

So far so good. However, native mode has a minimum signaling rate (DS892 Table 24) of 300 Mbps (RX DDR) or 150 MHz (RX SDR). This minimum rate is associated with the path through the PLL (e.g. CLKOUTPHY).

Two questions:

  • It must be possible to use "native mode" at lower clock rates, since that is effectively what "component mode" does. How?
  • Can QBC/DBC be used as capture clocks at DDR rates below 300 MHz by avoiding the PLL? We do not need its jitter-cleaning capabilities and would prefer to avoid the extra power dissipation.

I have reviewed DS892, UG571, and XAPP1274 in detail but can't find any hints.

Thanks!

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sandrao
Community Manager
Community Manager
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Registered: ‎08-08-2007

Hi @gsmecher

 

It is NOT possible.

You do not need a PLL in Component mode. As I said you can use the BUFG & BUFGCE_DIV in parallel to clock the CLK & CLKDIV of the ISERDES/OSERDES.

Thanks,

Sandy


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sandrao
Community Manager
Community Manager
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Registered: ‎08-08-2007

Hi @gsmecher 

 

Component Mode is a software abstraction of the Native Mode. It is not possible to use the "Native Mode" (RXTX_BITSLICE) at lower rates as this requires the CLKOUTPHY of the PLL.

If you need to go slower and move to Component Mode = ISERDES/OSERDES then a different clocking structure is implemented. The ISERDES/OSERDES is the software abstraction of the RXTX_BITSLICE with the clocking structure setup to come from other than the CLKOUTPHY. 

In Component Mode you do need to use a _GC pin to ensure you clock is routed on clock routing. If you do not need the PLL you can use a BUFG & BUFGCE_DIV in parallel to clock the CLK & CLKDIV of the ISERDES/OSERDES. 

Thanks,

Sandy


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gsmecher
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Registered: ‎01-21-2011

Hi Sandy,

Thanks: your description matches my understanding, but I doesn't directly tackle my question.

We have a hardware design that can be made to work with component primitives (using a nearby GC), but which would be cleaner if we could use DBC/QBC as a capture clock below the minimum rate supported by native mode (280 Mbps / 140 MHz DDR in this case).

It's a receive-only interface with a center-aligned capture clock at DBC/QBC, which is about as simple as it gets. Even if the data rate was high enough to meet the minimum RX_BITSLICE frequency, we'd prefer to save the power and avoid the PLL.

I'm wondering if this configuration is possible. It's certainly not documented and I realize we're a little off-piste. However, with the sole exception of the minimum-frequency-requirement we're a perfect match for RX_BITSLICE and I'd like to chase this possibility down further.

best,
Graeme

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sandrao
Community Manager
Community Manager
559 Views
Registered: ‎08-08-2007

Hi @gsmecher

 

It is NOT possible.

You do not need a PLL in Component mode. As I said you can use the BUFG & BUFGCE_DIV in parallel to clock the CLK & CLKDIV of the ISERDES/OSERDES.

Thanks,

Sandy


------------------------------------------------------------------------------------------------

Don’t forget to reply, kudo, and accept as solution.

If starting with Versal take a look at our Versal Design Process Hub , Versal Blogs and the Versal Useful Resources .

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gsmecher
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Registered: ‎01-21-2011

Perfect. Thanks for being unequivocal.

cheers,
Graeme

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