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m006
Voyager
Voyager
8,344 Views
Registered: ‎03-18-2008

Ultrascale+ DPHY IO from PG202

Can the data/clk lane IO be any bank LVDS IO?

 

Or, is it any GTH serdes IO?

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1 Reply
trenz-al
Scholar
Scholar
8,255 Views
Registered: ‎11-09-2013

MIPI IP Core has very strict placement, so ALL pins not only clock are locked to fixed places in the bank