What exactly is meant by the 100% step load assumption for VCCAUX/VCCAUX_IO in UG583 for ultrascale+ (pg 19)? Xilinx power estimator is given me a ~700mA expected combined current for VCCAUX+VCCAUX_IO (XCZU29DR-FFVF1760), and the recommended rail limits are 1.746V to 1.854V (+/-54mV) per DS926 pg 4. Per UG583 pg 146 I only need 1x 47uF and 1x 4.7uF (~51uF total) capacitor on these rails.
Small ripple approximation: I=C(dv/dt) -> DT = C*DV/I
Plugging in the 51uF capacitance, 700mA load step, and 54mV voltage excursion implies a capacitance hold up time of only 3.93us. Is the expectation that our VCCAUX/VCCAUX_IO regulator has sufficient loop gain at ~250KHz to react to such a short hold up? I realize I could just add more load capacitance / find a faster voltage regulator but I am a little bit worried that I am missing something fundamental here.
- A real capacitor at its operating voltage will have less effective capacitance
- capacitance will also decrease with temperature, as it's not unusual to find these capacitors at 40-50 C
- Real capacitors have a small series resistance and inductance that becomes significant at high frequencies.
- Plane and PCB traces resistance and inductance, including vias and IC balls, are not negligible
The key of voltage regulation lies on the regulator not on the caps. Regulation is an active process, capacitors only balance it. Adding "more caps" won't probably solve anything. You will certainly soften the voltage dips but worsen the overshoots, and that's exactly what kills ICs! You will never stress an IC with undervoltages, right? So, caps (the low freq ones), just the minimum.