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psarg
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Registered: ‎10-04-2019

Ultrascale+ XADC non-linearity

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Dear all,

I have found what I believe is an error / non-linearity in the response of the XADC on an XCZU5EV Ultrascale+ part.

I am using an XCZU5EV Ultrascale+ part in a design. I use a number of the ADxP inputs to monitor various voltages around the board. I have these inputs configured as "unipolar" inputs with AD8N connected to GND and used as the "common n" ground reference.

We have prototype boards back from manufacture and I have been testing these. My understanding is that the input range I can apply to the ADxP pins is 0.00 to 1.00v. After careful measurement, I find that the XADC returns the correct / expected values for input voltages up to about 0.65v. However, as the input voltage increases above 0.65v, the value returned by the XADC becomes increasingly errored. So, with a 0.65v input, the XADC returns the expected 0.65v. However, with a 1.00v input, the XDAC returns a value that is significantly less than the expected 1.00. I have plotted the actual vs measured response in the attached graph. The non-linearity above 0.65v is very obvious.

A constant error could be explained as a DC offset. A linear error could be explained as too high a source resistance. However, I am struggling to explain this apparent non-linear behaviour above 0.65v. Anyone got any thoughts?

Thank you! Peter

XADC_response_expected_vs_actual.png
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psarg
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Registered: ‎10-04-2019

Well done Tenzinc! Yes, I think you have identified the cause of the problem. As you predicted, there are indeed unused IO banks in our design and their VCCO pins are connected to ground. Unfortunately it is not possible for me to modify our PCBs in order to disconnect these pins from GND so I cannot verify that doing this fixes the problem. However, this does sound like the probable cause, especially as I notice Xilinx specifically added the sentence you highlighted to UG583 in the 26th November 2019 update of that document. So I guess this was an unforeseen problem  that only came to the attention of Xilinx relatively recently.

Meanwhile, I can work around this problem on my current boards by adjusting resistor values to restrict the voltage range of vauxp pins to 0 - 0.65v since the ADC appears to work accurately over that range. I will also modify our design files so that the VCCO pins of unused banks are connected to 1v8 instead of GND. Hopefully that will fix the issue on future builds of our boards.

So my thanks to you and also to Mark for your prompt and helpful replies. This was my first use of the Xilinx Community Forum and it has been a very enjoyable and positive experience!

Thanks again, Peter

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6 Replies
1,440 Views
Registered: ‎01-22-2015

Hi Peter,

Welcome to the Forum! 

Back when it was called the XADC, things were simpler.  However, for the XCZU5EV, it is called the SYSMONE4 and things are now a little different (see Table 1-1 in UG580(v1.9.1)).

Some questions for you:

Q1:  Are you using the on-chip or off-chip reference?  - and have you got things connected per Figure 1-3 in UG580?

Q2:  I assume you are using the System Management Wizard (ref document PG185) to setup the SYSMONE4/XADC.  Have you let this wizard write all the constraints for the SYSMONE4 – or have you written some constraints on your own and placed them in the Vivado .xdc file?

Q3: What is value of VCCO for the FPGA bank that contains the analog input pins to SYSMONE4?

Q4: For the vauxp/vauxn inputs, is your “Common-N” pin tied directly to ground or through a resistor to ground?

Q5: During your test, did you ensure that ALL vauxp/vauxn inputs were within the 0-1V range – and not just the channel you were testing?

Q6: Please show us the complete circuit you are using to feed an analog voltage to one the vauxp/vauxn inputs.

Cheers,
Mark

psarg
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Registered: ‎10-04-2019

Hi Mark,

Many thanks for your prompt reply. Here are the answers to the questions you asked:

A1. I am using on-chip reference. Our circuit implementation is identical to that shown in UG580 figure 1-3 for "Using On-Chip Reference".

A2. Yes, I am using the System Management Wizard to setup the SYSMONE4/XADC and use the constraints generated by this wizard. I have not written my own constraints with the exception of assigning the IOSTANDARD of the vauxp pins. Here I have assigned the vauxp pins that I am using as inputs for the (unipolar) voltages to be monitored as "ANALOG_SE" and vaux8p (which is my "Common-N" input) as "ANALOG".

A3. The value of VCCO for the FPGA bank that contains the analog input pins to SYSMONE4 is 1.8v.

A4. I am using vaux8n as my "Common-N" pin. I have this connected directly to ground. However, I recognised the fact that this might not be ideal, so I already tried the following experiment: I managed to cut the connection between the Common-N pin and GND and I was able to insert a 1k resistor. I then connected a pure voltage source (actually a low voltage bench power supply) again via a 1k resistor to pin vaux0p giving me the ability to vary the voltage on this pin over the full 0.00 to 1.00v range. The key point here is that both vaux8n (Common-N) and the vaux0p pin "saw" an identical 1k series resistance. However, this made no difference and I still observed an increasing error in the value returned from the ADC as the input voltage rose above 0.65v (as illustrated in the graph I presented previously).

A5. For my test, I had the following vauxp pins defined as unipolar, "Common-N" inputs and enabled via the "External Channel Selection" tab of the System Management Wizard: vaux0p, vaux9p, vaux10p. Additionally, vaux8p/n is enabled and specified in the "Common N Source Selection" field. I can guarantee that all vaux0p, vaux8p, vaux9p and vaux10p pins were within the 0-1v range (and not just the channel I was testing = vaux0p). However (and to be clear), I am using some other vauxp/n pins as 1.8v digital IO hence some of these pins may have been at 1.8v.

A6. I attach the circuit. This is a bit of a "hack" as I had to pull together various bits of circuitry from separate schematic sheets. However, I think it shows sufficiently well how I have the various vauxp/n pins connected. As I mentioned previously, the key pins of interest are:

  • vaux0p (signal DCIN_MONITOR) which connects via a potential divider (also shown in the clip) to the main DC input power rail (8 to 20v).
  • vaux8n used as Common-N connection.
  • vaux9p (signal RFB_ID) which connects via a potential divider (also shown in the clip) to the 1.8v rail. Clearly, with 2x 10k resistors, we expect the voltage presented to the vaux9p pin to be 1.8 / 2 = 0.900v. This may seem a little pointless, however, the idea is that connection of various daughter boards will place an additional resistor in parallel with the bottom 10k resistor which will reduce the voltage on the vaux9p pin and allow the software to figure out which variant of daughter board has been connected by measurement of the voltage. However, no daughter boards were connected during my board test so the expected voltage on this pin is 0.900v.
  • vaux10p (signal FPB_ID) same as vaux9p described above (but for version detection of a different daughter board).

These are the pins I had enabled (via the External Channel Selection tab of the System Management Wizard) for my board test. However, you will see there are other vauxp pins (vaux1p, vaux3p, vaux6p, vaux8p) that may also be enabled to perform voltage monitoring functions. Indeed it was the voltages measured by the ADC on pins vaux6p, vaux9p and vaux10p that first alerted me to this problem: All these inputs should return 0.900v. Yet the ADC returns a value of 0.811v for these pins! However, when I reduce the voltage on these pins to below 0.65v, the error goes away and the measurement returned by the ADC is accurate.

A final thought...  As noted, I find the ADC goes non-linear above 0.65v input voltage. It almost feels like one of the input protection diodes has started to conduct at this point. After all, I'm sure we all remember from our electronics courses that a typical silicon diode begins to conduct when Vbias gets to about 0.65v. Perhaps I have my vauxp pin configuration wrong in some way?

Thanks for your help, Peter.

 

Circuit.PNG
1,364 Views
Registered: ‎01-22-2015


Kudos to you for awesome answers and analysis.

Some more things to check/try:

  1. Please measure VCCO_64 and verify that it is 1.8V.

  2. Please remove all constraints that you have written for the vaux inputs being used as analog inputs.  The System Management Wizard should have written them for you.  You can open the special .xdc file shown below that was created by the wizard to verify that the constraints have been written for you.
    sys_manag_wiz.jpg

  3. I agree with you that this looks like an IO protection diode has started to conduct.   Although, this should not be happening.  However, along these lines, can you try driving one of the analog inputs from a low-impedance source and see if the nonlinearity remains?   For example, at your DCIN port, can your remove the 2K resistor, replace the 47K resistor with 100 ohms and drive DCIN with an op-amp or a variable voltage source with low impedance.
tenzinc
Moderator
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1,335 Views
Registered: ‎09-18-2014

Psarg,

 

I've seen this before on a few designs. This is an known issue with Xilinx Ultrascale/+ parts and it's covered under the "Unconnected VCCO Pins" section in UG583. I am fairly positive you have an grounded/unconnected IO bank on your device.  As you've seen it looks like a protection diode curve and there is a good reason for that. Each IO bank is equipped with these diodes and with how the SYSMON VAUX inputs are implemented within Ultrascale/+ not having the banks powered effects the VAUX input accuracy. 

unused vcco.JPG

Regards,

T



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psarg
Visitor
Visitor
1,305 Views
Registered: ‎10-04-2019

Well done Tenzinc! Yes, I think you have identified the cause of the problem. As you predicted, there are indeed unused IO banks in our design and their VCCO pins are connected to ground. Unfortunately it is not possible for me to modify our PCBs in order to disconnect these pins from GND so I cannot verify that doing this fixes the problem. However, this does sound like the probable cause, especially as I notice Xilinx specifically added the sentence you highlighted to UG583 in the 26th November 2019 update of that document. So I guess this was an unforeseen problem  that only came to the attention of Xilinx relatively recently.

Meanwhile, I can work around this problem on my current boards by adjusting resistor values to restrict the voltage range of vauxp pins to 0 - 0.65v since the ADC appears to work accurately over that range. I will also modify our design files so that the VCCO pins of unused banks are connected to 1v8 instead of GND. Hopefully that will fix the issue on future builds of our boards.

So my thanks to you and also to Mark for your prompt and helpful replies. This was my first use of the Xilinx Community Forum and it has been a very enjoyable and positive experience!

Thanks again, Peter

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tenzinc
Moderator
Moderator
1,247 Views
Registered: ‎09-18-2014

Psarg,

 

Yes the simplest workaround is to adjust the resistor divider to use the range between 0 to 0.65V or even 0.7V depending on the accuracy you can tolerate for your implementation. Thank you for your great information output which enabled an easy and fast elimination of possible causes to get to the real root cause. Your informative posts are a model to be shown for other posters using the forums.  

 

Regards,

T



Don’t forget to reply, kudo, and accept as solution.

Get started FAST with our UltraFAST design methodoly guides and don't forget to visit our Xilinx Design Hubs for additional resources and reference.

If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs

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