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Newbie
Newbie
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Registered: ‎10-17-2019

Unable to get rx_bitslip_sync_done from Rx HSSIO IP from Xilinx in Virtex Ultrascle FPGA in simulation

Hi All,

I have to run the LVDS link between 2 FPGAs. For this, I have used the HSSIO wizard from Xilinx IP Manager. As I am not receiving the CLK on the Rx side (Async Data Capture), I thought of using the in-built training & bit slip functionality of the HSSIO wizard configured in Async data capture mode for the Rx. 

I am running Tx at 8:1 serialization and Rx at 1:4 deserialization. I forced "0x2C" as a training pattern on the data from fabric(parallel data) from the Tx side. On the receiver, however, I am not able to get rx_bitslip_sync_done to indicate that the training pattern is received. It remains zero. 

Any idea as to how the "start bit slip" pin has to be used in order to get the status of training?

And is this pin active low or active high?

Also, when do we have to assert/de-assert this pin (some dependency on reset)?

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Community Manager
Community Manager
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Registered: ‎08-08-2007

Hi @dracula_786 

 

If you are using the Wizard in Async Data Capture its important to take note that the Wizard does not insert the CDR logic. 

I would suggest using Xapp1330 as a reference. It has good details on how to connect up to the Wizard ports and how to drive the logic.

https://www.xilinx.com/support/documentation/application_notes/xapp1330-async-data-capture-hssio.pdf

Thanks,
Sandy

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