UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer jineshjhonsa
Observer
494 Views
Registered: ‎10-21-2018

Unspecified I/O Standard: error with xdc in Zynq RFSOC

Jump to solution

Hi,
I am new to RFSOC chip.I am trying to run example design by right clicking on IP for Zynq RFSOC data converter.On Implementation I am getting following error. What should be the XDC ports for smartconnects connection of s_axi. Should I uncomment Bank 84,87,224,225,226,227,228,229 in ZCU 111 XDC file and add it? Please let me know. I have attached the block diagram.

 

 

[DRC NSTD-1] Unspecified I/O Standard: 127 out of 133 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: irq, s_axi_aresetn, adc0_axis_aresetn, s_axi_bresp[1:0], s_axi_araddr[23], s_axi_araddr[22], s_axi_araddr[21], s_axi_araddr[20], s_axi_araddr[19], s_axi_araddr[18], s_axi_araddr[17], s_axi_araddr[16], s_axi_araddr[15], s_axi_araddr[14], s_axi_araddr[13]... and (the first 15 of 63 listed).
[DRC UCIO-1] Unconstrained Logical Port: 127 out of 133 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: irq, s_axi_aresetn, adc0_axis_aresetn, s_axi_bresp[1:0], s_axi_araddr[23], s_axi_araddr[22], s_axi_araddr[21], s_axi_araddr[20], s_axi_araddr[19], s_axi_araddr[18], s_axi_araddr[17], s_axi_araddr[16], s_axi_araddr[15], s_axi_araddr[14], s_axi_araddr[13]... and (the first 15 of 63 listed).
Pin PlanningDRC

0 Kudos
1 Solution
1 Reply