07-07-2018 06:04 AM
I'm using one of the VRP pins, in a bank not utilizing DCI, as an output in a design on an ultrascale part. My understanding is that there is no issue with this configuration. However, I later found a note from Xilinx in a app note that says using VRP as i/o should be a last resort and may make impedance unstable in the bank - it isn't clear if that note only pertains to DCI or if it's applicable to general use. Can anyone clarify this point? Are there any consequences of using VRP as general i/o when not using DCI? Does anything special have to be configured so that VRP will work as an i/o?
07-07-2018 07:27 AM
This is what I came across
"With DCI disabled, the VRP pin, in each bank can be used as a single ended I/O, however impedance control and termination for all I/O within the bank will be very poor and therefore should be used as a last resort for additional I/O. DCI is disabled by setting the DCITERMDISABLE flag = 1"
07-07-2018 07:40 AM
Yes, if you require DCI in that bank, then using the VRP as IO will interfere with that. But, other than that obvious case, is that note from a UltraScale document?
07-07-2018 07:43 AM
It was provided to me by a colleague. I'll have to double check. But since I'm not using DCI, using VRP as i/o should be completely fine, right?