02-22-2019 08:40 AM
If I have a SERDES+PS-IO only design for a Zynq US+/RFSoC, is it possible to leave VCCAUX_IO unpowered / 0V? (I realize this may have ESD implications, but if I'm planning on floating the IO backs and just using GTs and PSIO, will I damage or otherwise cause problems).
My initial understanding is that this is OK (as long as VCCO is also 0V and I ensure that I do not accidentally backpower through the IO pins). Am I correct in this assumption?
02-24-2019 10:17 PM
@ryukich DS926 Zynq UltraScale+ RFSoC Data Sheet mentions "VCCAUX_IO must be connected to VCCAUX" under Table 1 and Table 2. I believe you are powering the VCCAUX which is needed since it powers some of the internal circuitry and so do tie VCCAUX_IO to VCCAUX as per recommendation.
02-24-2019 10:17 PM
@ryukich DS926 Zynq UltraScale+ RFSoC Data Sheet mentions "VCCAUX_IO must be connected to VCCAUX" under Table 1 and Table 2. I believe you are powering the VCCAUX which is needed since it powers some of the internal circuitry and so do tie VCCAUX_IO to VCCAUX as per recommendation.