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Contributor
Contributor
3,844 Views
Registered: ‎06-16-2017

VRN & VRP

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Hi,

 

I am doing a design with a Zynq XC7Z007S-1CLG400 and was surprised to see that two signals related to the DDR seemed to be inverted.  The datasheet(s) tell me to connect PS_DDR_VRN_502 to VCCO_DDR_502 through a pull-up resistor and PS_DDR_VRP_502 to GND through a pull-up resistor.

 

In every other instance that I can think of, any signal that ends in "N" is associated with GND and signals that end in "P" are associated with some positive voltage.

 

So, I have a couple of questions (because I had these swapped and caught it just before we went to layout!):
1) Why did Xilinx stray from their standard on these two pins?

2) Would it still work if I connected them "backwards"?

 

Thanks,

Dan

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Professor
Professor
6,003 Views
Registered: ‎08-14-2007

These signals have been defined this way since Xilinx introduced DCI (with Virtex II if I remember correctly).  VRN is a NFET that drives low against a pull-up (open drain) and VRP is a PFET that drives high against a pull-down.  These are used to calibrate the drive current for matching FETs in the output drivers that use the DCI standard.  So VRN trims the current drive for outputs when they drive low and VRP trims the current drive for outputs when they drive high.  The naming comvention has caused many a board layout error, but once you understand the reason it makes sense.

-- Gabor

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Professor
Professor
6,004 Views
Registered: ‎08-14-2007

These signals have been defined this way since Xilinx introduced DCI (with Virtex II if I remember correctly).  VRN is a NFET that drives low against a pull-up (open drain) and VRP is a PFET that drives high against a pull-down.  These are used to calibrate the drive current for matching FETs in the output drivers that use the DCI standard.  So VRN trims the current drive for outputs when they drive low and VRP trims the current drive for outputs when they drive high.  The naming comvention has caused many a board layout error, but once you understand the reason it makes sense.

-- Gabor

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Contributor
Contributor
3,727 Views
Registered: ‎06-16-2017

Hi Gszakacs,

 

Thanks for the reply and the explanation. I am hopeful that Xilinx will do better as they go forward.

 

Thanks,
Dan

 

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