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Visitor bob_w
Visitor
397 Views
Registered: ‎05-18-2018

VU37P HBM Power Rail Decoupling

I am using an Ultrascale+ Vu37P, it has 8GB of DRAM.  I have looked at the VCU128 eval schematics, and the latest (Jan 2019) UG583 PCB design guide to figure out the decoupling capacitor requirements.  The VCU128 I assume was designed awhile ago perhaps when still proving out the design and they weren't sure how much decoupling was required because it has many more caps that are recommended in UG583 (Table 1-9).  Also UG583 Table 1-9 confuses me because I don't know if it is for 4Gb and I should double it for 8Gb part or it covers both.  A little clarification would help me get the correct decoupling for the HBM rails.

Thanks

Bpb

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Xilinx Employee
Xilinx Employee
329 Views
Registered: ‎07-23-2015

Re: VU37P HBM Power Rail Decoupling

@bob_w You are right in that Eval boards are designed well before the chip arrives and so tend to be overdesigned wrt decoupling. UG583 is based on characterization results and so it should be the guide you follow. 

Table 1-9 covers both since if you notice unlike Table 1-8 which list the individual devices, Tbale 1-9 doesn't list out any device and so covers HBM rails for all devices. 

- Giri
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Visitor bob_w
Visitor
287 Views
Registered: ‎05-18-2018

Re: VU37P HBM Power Rail Decoupling

That implies that the guy that uses the smaller 4GB part has 2x the decoupling necessary.  You need to update the guide so it is clear!

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