cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
hithesh123
Contributor
Contributor
2,934 Views
Registered: ‎12-06-2017

Vref pin on Ultrascale

Jump to solution

What is the current requirement for the Vref pin on Ultrascale FPGAs.

Does it require a mA of current.

Is it similar to DDR VrefCA pin?

0 Kudos
1 Solution

Accepted Solutions
umamahe
Xilinx Employee
Xilinx Employee
3,747 Views
Registered: ‎08-01-2012

It is in uA (Micro Amperes) range. The value specified in relevant ultrascale device data sheet  Table 3: DC Characteristics Over Recommended Operating Conditions.  For example for Kintex ultrascale IRef currrent per pin is 15 uA. 

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

Give kudos to this post in case if you think the information is useful and reply oriented.

View solution in original post

6 Replies
umamahe
Xilinx Employee
Xilinx Employee
3,748 Views
Registered: ‎08-01-2012

It is in uA (Micro Amperes) range. The value specified in relevant ultrascale device data sheet  Table 3: DC Characteristics Over Recommended Operating Conditions.  For example for Kintex ultrascale IRef currrent per pin is 15 uA. 

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

Give kudos to this post in case if you think the information is useful and reply oriented.

View solution in original post

hithesh123
Contributor
Contributor
2,865 Views
Registered: ‎12-06-2017

Followup: are there any advantages of using external vs internal Vref?

0 Kudos
umamahe
Xilinx Employee
Xilinx Employee
2,859 Views
Registered: ‎08-01-2012

 

@hithesh123

Internal generation removes the need to provide for a particular VREF supply rail on the printed circuit board (PCB). The internally generated VREF (INTERNAL_VREF) is sourced from the VCCO. That is the advantage of Internal Vref pin. 

 

The trade of is that the Valid settings of INTERNAL_VREF are listed. Not all values are supported in all types of banks:Also external Vref is more accurate and do not depend upon of VCCO stability.  This is bet demerit compare to external Vref usage. So based on application requirement customer need to choose right one. 

 

 

FYI:

1) Please note that Internal VREF (INTERNAL_VREF and VREF scan) cannot be combined with external VREF usage within a bank.

2) VREF is a dedicated pin and cannot be used as a normal I/O pin even when
INTERNAL_VREF is used.

 

Kind Request: If there are any follow on questions with regards to this issue please post a new query instead of posting in closed forum post. For reference purpose if you wish you may add this old forum link in your new forum post query. That is the guidelines for Forum users. 

________________________________________________

Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

Give kudos to this post in case if you think the information is useful and reply oriented.

0 Kudos
hithesh123
Contributor
Contributor
2,666 Views
Registered: ‎12-06-2017

Is it mandatory to use Internal Vref?

0 Kudos
gnarahar
Moderator
Moderator
2,655 Views
Registered: ‎07-23-2015

@hithesh123 Depends on your application. If using Memory IP, Internal VREF is always used for DDR4 while it is optional for DDR3

- Giri
------------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
------------------------------------------------------------------------------------------------------------------------

0 Kudos
hithesh123
Contributor
Contributor
2,649 Views
Registered: ‎12-06-2017

Thanks. I missed this in the UG583 DDR PCB design guide.

Is this mentioned anywhere other than Memory IP docs?

0 Kudos