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1,299 Views
Registered: ‎04-11-2017

What is the maximum frequency we can have for our design on xillinx fpga's ?

Hi,

I have a requirement of 900Mhz clock is this possible on fpga's ? My design currently suts on ZCU 102

 

Thanks,
Anjaneyulu

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1,283 Views
Registered: ‎01-16-2013

@anjaneyulu.challa9,

 

Check the following forum discussion: 

https://forums.xilinx.com/t5/Welcome-Join/Maximum-frequency-of-Device/td-p/697099

 

Please create a design and see the maximum operating frequency of the design from timing analysis. 

 

--Syed

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Did you check our new quick reference timing closure guide (UG1292)?
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1,188 Views
Registered: ‎06-21-2017

The data sheet indicates that the Fmax for a global clock tree or DSP slice is 891MHz for a -3 part running at 0.9V.  For a ZCU-102, I think it is a -2 part at 0.85V.  This has an Fmax of 775MHz..  If your clock requirement is for anything in the FPGA fabric, and not just a gigabit transceiver, you should re-think the design. 

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Registered: ‎04-11-2017

If your clock requirement is for anything in the FPGA fabric, and not just a gigabit transceiver, you should re-think the design

Sorry I did'nt get that
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