07-10-2018 08:44 PM
07-10-2018 09:17 PM
Check the following forum discussion:
Please create a design and see the maximum operating frequency of the design from timing analysis.
07-12-2018 06:46 AM
The data sheet indicates that the Fmax for a global clock tree or DSP slice is 891MHz for a -3 part running at 0.9V. For a ZCU-102, I think it is a -2 part at 0.85V. This has an Fmax of 775MHz.. If your clock requirement is for anything in the FPGA fabric, and not just a gigabit transceiver, you should re-think the design.
07-12-2018 09:33 PM