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rmillet
Visitor
Visitor
2,275 Views
Registered: ‎05-30-2017

XCZU9: CMT ressources utilization using HDMI IP

Hi all,

 

I'm working on the new ZCU102 (ES2) development kit and I would like to implement a pretty big design using multiple transceiver banks.

 

I made a design with 2 Xilinx HDMI SS RX IPs and 2 Xilinx HDMI SS TX IPs using embedded HDMI RX/TX connectors + 1 FMC module. These IPs are connected to 2 Video PHY IPs (RX + TX links each).

 

This design use the 4 available MMCM ressources of the ZYNQ.

 

I would like to add 2 to 4 independant SDI serial links connected on the same bank (SFP interfaces available on the board).

 

I suppose this PHY bank will need a CMT ressource available.

 

Is there a way to share the MMCM ressources between the PHY or a solution to use other transceiver banks?

 

Thanks.

Raphael

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jheslip
Xilinx Employee
Xilinx Employee
2,251 Views
Registered: ‎06-30-2010

this is more an IP question, it is certainly possible to share the MMCM / PLL outputs to multiple cores. The question is if the cores you are using will allow this and if the clock rates / phases are supported. Can you post to Ip forumn
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