06-09-2016 11:52 PM
DS923 page 9 and DS922 page 8 shows the that the FPGA has a recommended power on and power off sequencing.
I would like to know, is it mandatory to have the power off sequence for the FPGA? Please confirm.
06-10-2016 06:41 AM
No, it is not. However, we test every part to these conditions. The other conditions are all characterized (verified to not be an issue). Only sequences specifically called out as "do not use" are prohibited. Last time I checked, I did not see anything like that in the data sheet. Please check the latest data sheet. If it is called out NOT to use, the do not use it. Otherwise, it is OK.
06-10-2016 08:32 AM
06-12-2016 11:26 PM
Thanks for the confirmation on power off sequence not being mandatory.
06-12-2016 11:52 PM
We have DS923 v1.0 datasheet and there is no specific mention of Power On or Power Off Sequencing as "Do Not Use". Does this mean that it is not mandatory to follow the recommended Power On Sequencing as well? Please clarify.
06-13-2016 06:52 AM
If there is no recommended sequence, then you may do what you wish. However, the production data sheet has always had the sequence we use to test every part, so I would caution you to either get the latest datasheet, or contact your Xilinx or distributor FAE.
There is always a recommended sequence. There may be other sequences that are prohibited. They are always in the datasheet once the family is in production. Devices are characterized for both on and off sequencing. Generally, on all at once, off all at once works. All at once is defined as all with a few milliseconds of each other achieving >90% of the recommended DC value for on, <10% for off.
06-14-2016 02:30 AM
Thanks for the reply.
In the VCU108 EVM, Xilinx has used power supply sequencer IC to control the power on and off sequence.
Due to lack of space on our board, we plan to do only the power on sequencing using Power Good outputs of one IC and connecting them to Enable input of other IC. By doing this, we will only be able to meet the power on and not the power off sequencing. We plan to do this for both UltraScale+ and UltraScale devices.
Do you see any issues with this scheme?
06-14-2016 06:41 AM
If you violate any specific requirement, there is no guarantee of operation, reliability.
For any specific sequence which violates the datasheet you may ask a Xilinx FAE for its effect.