11-27-2020 03:47 AM
Hello
The following is a design where in I am trying to feed RFSoC DAC with a sine wave input from DDS IP. Each of the individual blocks are configured as shown below figures. Before dumping the system on to FPGA, I am trying to test its working by writing a test bench in Verilog. How to declare dac1_clk, sysref_in and clk in test bench. dac1_clk in the wrapper is divided as dac1_clk_n and dac1_clk_p. Same is the case with sysref_in and vout also. How to define and assign values to them in a test bench and observer them.?
The Design Wrapper has the following Code -
`timescale 1 ps / 1 ps
module design_2_wrapper
(clk,
dac1_clk_clk_n,
dac1_clk_clk_p,
reset,
sysref_in_diff_n,
sysref_in_diff_p,
vout12_v_n,
vout12_v_p);
input clk;
input dac1_clk_clk_n;
input dac1_clk_clk_p;
input reset;
input sysref_in_diff_n;
input sysref_in_diff_p;
output vout12_v_n;
output vout12_v_p;
wire clk;
wire dac1_clk_clk_n;
wire dac1_clk_clk_p;
wire reset;
wire sysref_in_diff_n;
wire sysref_in_diff_p;
wire vout12_v_n;
wire vout12_v_p;
design_2 design_2_i
(.clk(clk),
.dac1_clk_clk_n(dac1_clk_clk_n),
.dac1_clk_clk_p(dac1_clk_clk_p),
.reset(reset),
.sysref_in_diff_n(sysref_in_diff_n),
.sysref_in_diff_p(sysref_in_diff_p),
.vout12_v_n(vout12_v_n),
.vout12_v_p(vout12_v_p));
endmodule
The Verilog Test Bench i wrote (partially complete) is as follows -
module test0_design2;
//Inputs
reg clk;
reg dac1_clk_clk_n;
reg dac1_clk_clk_p;
reg reset;
reg sysref_in_diff_n;
reg sysref_in_diff_p;
//Outputs
wire vout12_v_n;
wire vout12_v_p;
//Instantiate the Unit Under Test (UUT)
design_2_wrapper uut1
(.clk(clk),
.dac1_clk_clk_n(dac1_clk_clk_n),
.dac1_clk_clk_p(dac1_clk_clk_p),
.reset(reset),
.sysref_in_diff_n(sysref_in_diff_n),
.sysref_in_diff_p(sysref_in_diff_p),
.vout12_v_n(vout12_v_n),
.vout12_v_p(vout12_v_p));
initial begin
// Initialize Inputs
reset=1;
#6500 reset=0;
end
always #5 clk=clk;
endmodule
Please Help.
11-30-2020 06:35 AM
Hi @ksram1988
These are differential clocks so you need to give stimulus for both.
As P and N are complementary to each other , you can define like below
This will generate 500MHz differential clock .
12-01-2020 06:37 AM
Hi @pthakare
Thanks for the reply. If dac1_clk_clk_n and dac1_clk_clk_p are set to 500MHz, what about sysref_in_diff_n and sysref_in_diff_p? What frequency they must be set to? Also, I set .clk to 100 MHz, is that right?
Please Reply
Thanking You
12-01-2020 07:10 AM
Hi @ksram1988
sysref_in_diff_n and sysref_in_diff_p is not needed in your case as you are not using the MTS functionality.
For MTS the requirements for SYSREF are documented in PG269
https://www.xilinx.com/support/documentation/ip_documentation/usp_rf_data_converter/v2_3/pg269-rf-data-converter.pdf -> page 124.
The .clk is will not generate if you dont toggle it .
use below code for 100MHz clock stimulus generation
initial begin
clk = 0;
forever begin
#5 clk = ~ clk;
end
end
Additionally for simulation you can simply generate the example design and see how stimulus are defined.
Example design is generate by right click to Ip-> Open example design
12-02-2020 02:09 AM
Hi @pthakare
I tried the test bench as you said. The following is my test bench.
initial begin
// Initialize Inputs
reset=1;
sysref_in_diff_n=0;
sysref_in_diff_p=1;
#20 reset=0;
end
initial begin
clk=0;
forever begin
#5 clk=~clk;
end
end
initial begin
dac1_clk_clk_n=1;
forever begin
#1 dac1_clk_clk_n=~dac1_clk_clk_n;
end
end
initial begin
dac1_clk_clk_p=0;
forever begin
#1 dac1_clk_clk_p=~dac1_clk_clk_p;
end
end
But I am not getting any signals on vout12_v_n and vout12_v_p. The following is my waveform. Where am I making mistake? Is there something wrong with the design itself?
12-02-2020 02:43 AM
Hi @ksram1988
The realtobits conversion is needed here.
Refer to the example design testbench or page 164 of product guide
12-02-2020 04:06 AM
Hi @pthakare
I tried realtobinary conversion and my testbench code is as follows
module test0_design2;
//Inputs
reg clk;
reg dac1_clk_clk_n;
reg dac1_clk_clk_p;
reg reset;
reg sysref_in_diff_n;
reg sysref_in_diff_p;
//Outputs
wire vout12_v_n;
wire vout12_v_p;
real dac01_p;
real dac01_n;
//Instantiate the Unit Under Test (UUT)
design_2_wrapper uut1
(.clk(clk),
.dac1_clk_clk_n(dac1_clk_clk_n),
.dac1_clk_clk_p(dac1_clk_clk_p),
.reset(reset),
.sysref_in_diff_n(sysref_in_diff_n),
.sysref_in_diff_p(sysref_in_diff_p),
.vout12_v_n(vout12_v_n),
.vout12_v_p(vout12_v_p));
initial begin
// Initialize Inputs
reset=1;
sysref_in_diff_n=0;
sysref_in_diff_p=1;
#20 reset=0;
end
initial begin
clk=0;
forever begin
#5 clk=~clk;
end
end
initial begin
dac1_clk_clk_n=1;
forever begin
#1 dac1_clk_clk_n=~dac1_clk_clk_n;
end
end
initial begin
dac1_clk_clk_p=0;
forever begin
#1 dac1_clk_clk_p=~dac1_clk_clk_p;
end
end
always@(*)
begin
dac01_p = design_2_wrapper.vout12_v_p;
dac01_n = design_2_wrapper.vout12_v_n;
force design_2_wrapper.vout12_v_p = $realtobits(dac01_p);
force design_2_wrapper.vout12_v_n = $realtobits(dac01_n);
end
endmodule
However, now I am getting all zero values in the simulation. Where am I making mistake?
12-04-2020 04:56 AM - edited 12-04-2020 05:04 AM
Hi @pthakare
Could you please look into the issue? Any inputs on understanding the verilog statements of real to binary conversion? Like these statements
// Map the RF-DAC signals to the top level
dac00_p =
DUT.i_rf_dut_block.inst.rf_dut_rf_wrapper_i.tx0_u_dac.SIP_HSDAC_INST.VOUT0_P
;
dac00_n =
DUT.i_rf_dut_block.inst.rf_dut_rf_wrapper_i.tx0_u_dac.SIP_HSDAC_INST.VOUT0_N
;
// force the RF-DAC output onto the RF-DAC sink
force dac_sink.vin_00_p = $realtobits(dac00_p);
force dac_sink.vin_00_n = $realtobits(dac00_n);
Regards