02-21-2019 05:20 AM
In UG583 Table 1-9 the recommended decoupling capacitors for Vccaux and Vccaux_io are combined in on table.
For our package the recommended caps are 1x 47uF and 2x 4.7uF.
Does this mean that Vccaux and Vccaux_io each need to have 3 caps? Or is it 3 caps for both rails combined?
02-21-2019 07:15 AM
Yes, if connected together, you still need all caps. It is energy stored to keep droop under transient load within specifications. These are for the lowest frequency dynamic loading, intended to meet almost all possible designs.
Is it over-kill for your design? Maybe. Probably. Could you get by with fewer capacitors? Maybe ...
Tier 1 customers (like Cisco) design their own power distribution networks to meet their needs. Takes lots of CAD tool work, pcb extraction, modeling ...
Bypassing recommendations from Xilinx come from many years of building development boards, not actual products.
02-21-2019 07:34 AM
When looking at the schematic (page 11) of the UltraZed EV board I can see only three caps (1x 47uF and 2x 4.7uF) being used for both Vccaux and Vccaux_io.
I think Vccaux/Vccaux_io being combined in the same column would be done like this to imply the same bypass caps are used for both rail.
But would like to be sure before I continue in the design.
02-21-2019 07:55 AM
As already highlighted, Decoupling, if in doubt , leave alone:
If you over decouple, the board costs might go up a little, and the BOM will go up a few extra capacitors. But decoupling wont be a problem.
If you under de couple, then yo uare in for a WORLD of pain.
The board could be intermitant, could work monday and not fridays, might be just fin , mos tof th etime, but fail in a year or two, intermitantly, and a board re spin would be need to fix it, IF you could find the reason.
Its your job, but I know if its mine, what route between following and cutting back on decouplng I'd go down unless I had VERY good reasons;