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Observer cmuhlbauer
Observer
1,145 Views
Registered: ‎02-14-2018

Zynq Ultrascale+ PS Bank 503 IBIS models

Why are there no models for the Zynq Ultrascale+ PS Bank 503 signals in either the downloaded or generated IBIS file?  What model should I use for the PS_REF_CLK, PS_JTAG_xxx, etc?

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4 Replies
Moderator
Moderator
1,138 Views
Registered: ‎04-18-2011

Re: Zynq Ultrascale+ PS Bank 503 IBIS models

I thought this worked before.
I should be LVCMOSXX_PSMIO.
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Moderator
Moderator
1,134 Views
Registered: ‎04-18-2011

Re: Zynq Ultrascale+ PS Bank 503 IBIS models

just tried this and you are correct. 

 

As a workaround:

 

use the -allmodels option to include all the models in the generated file

 

write_ibis ./test.ibs -allmodels -truncate 40 -force

 

This will include every model available.

 

Then manually assign the correct model to the PS_REFCLK pin in the pinout section. 

 

PS-REFCLK uses LVCMOS input and the voltage is the same as the VCCO_MIO0

 

Use this mapping to select the correct model

 

4001 PS_MIO_LVCMOS18_F_2 M0_PADH_02_F_NA_PBIDIR_18_18_NT_DR_H
4002 PS_MIO_LVCMOS18_S_2 M3_PADH_02_S_NA_PBIDIR_18_18_NT_DR_H
4003 PS_MIO_LVCMOS18_F_4 M6_PADH_04_F_NA_PBIDIR_18_18_NT_DR_H
4004 PS_MIO_LVCMOS18_S_4 M9_PADH_04_S_NA_PBIDIR_18_18_NT_DR_H
4005 PS_MIO_LVCMOS18_F_8 M12_PADH_08_F_NA_PBIDIR_18_18_NT_DR_H
4006 PS_MIO_LVCMOS18_S_8 M15_PADH_08_S_NA_PBIDIR_18_18_NT_DR_H
4007 PS_MIO_LVCMOS18_F_12 M18_PADH_12_F_NA_PBIDIR_18_18_NT_DR_H
4008 PS_MIO_LVCMOS18_S_12 M21_PADH_12_S_NA_PBIDIR_18_18_NT_DR_H
4011 PS_MIO_LVCMOS25_F_2 M0_PADH_02_F_NA_PBIDIR_25_25_NT_DR_H
4012 PS_MIO_LVCMOS25_S_2 M3_PADH_02_S_NA_PBIDIR_25_25_NT_DR_H
4013 PS_MIO_LVCMOS25_F_4 M6_PADH_04_F_NA_PBIDIR_25_25_NT_DR_H
4014 PS_MIO_LVCMOS25_S_4 M9_PADH_04_S_NA_PBIDIR_25_25_NT_DR_H
4015 PS_MIO_LVCMOS25_F_8 M12_PADH_08_F_NA_PBIDIR_25_25_NT_DR_H
4016 PS_MIO_LVCMOS25_S_8 M15_PADH_08_S_NA_PBIDIR_25_25_NT_DR_H
4017 PS_MIO_LVCMOS25_F_12 M18_PADH_12_F_NA_PBIDIR_25_25_NT_DR_H
4018 PS_MIO_LVCMOS25_S_12 M21_PADH_12_S_NA_PBIDIR_25_25_NT_DR_H
4021 PS_MIO_LVCMOS33_F_2 M0_PADH_02_F_NA_PBIDIR_33_33_NT_DR_H
4022 PS_MIO_LVCMOS33_S_2 M3_PADH_02_S_NA_PBIDIR_33_33_NT_DR_H
4023 PS_MIO_LVCMOS33_F_4 M6_PADH_04_F_NA_PBIDIR_33_33_NT_DR_H
4024 PS_MIO_LVCMOS33_S_4 M9_PADH_04_S_NA_PBIDIR_33_33_NT_DR_H
4025 PS_MIO_LVCMOS33_F_8 M12_PADH_08_F_NA_PBIDIR_33_33_NT_DR_H
4026 PS_MIO_LVCMOS33_S_8 M15_PADH_08_S_NA_PBIDIR_33_33_NT_DR_H
4027 PS_MIO_LVCMOS33_F_12 M18_PADH_12_F_NA_PBIDIR_33_33_NT_DR_H
4028 PS_MIO_LVCMOS33_S_12 M21_PADH_12_S_NA_PBIDIR_33_33_NT_DR_H

 

 

 

 

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Observer cmuhlbauer
Observer
1,030 Views
Registered: ‎02-14-2018

Re: Zynq Ultrascale+ PS Bank 503 IBIS models

What about the JTAG signals?  Should I use the LVCMOS models too?  What is the drive and slew for TDO?

 

"PS-REFCLK uses LVCMOS input and the voltage is the same as the VCCO_MIO0"?  VCCO_MIO0 is not a pin name on this part.  All other documents indicate PS_REF_CLK is powered by VCCO_PSIO3_503.

 

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Moderator
Moderator
1,024 Views
Registered: ‎04-18-2011

Re: Zynq Ultrascale+ PS Bank 503 IBIS models

Sorry, you are correct it should match VCCO_PSIO3_503.
JTAG signals should be LVCMOS also.
I expect these to be 8mA drive. I will check.
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