07-25-2019 09:06 PM - edited 07-25-2019 09:23 PM
Is there any way we can Bypass the FIFO in RX BITSLICE?
I am using SelectIO primitives as native mode and this FIFO is causing additional latency in my design which I do not want(My design is application specific).
Any expert please?
07-29-2019 01:16 AM
Unfortunately it is not supported to Bypass the FIFO in the RX_BITSLICE.
10-15-2019 12:51 AM
@sandraoDocumentation not updated as usual.
pg188 v3.5 p.33:
Enables Register Interface Unit (RIU) for each bytegroup to access internal registers. Every
delay element tap setting can be read with the RIU. Various features, such as clock gating
and Voltage Temperature (VT) tracking, can be disabled. With this option, you can
dynamically change the FIFO usage (for example, from synchronous to asynchronous to full
bypass). It enables the RIU access, but does not add additional logic for RIU access
10-15-2019 03:27 AM
Thanks for the heads up, I just filed a Change Request against PG188 to have the FIFO Bypass reference removed.
10-17-2019 08:28 PM
I just want to point out that you can use the I/O in component mode, where you have the choice of using the FIFO or not (the FIFO can definitely be disabled in component mode).
Of course, this completely changes the interfaces - there are many features of native mode that aren't available in component mode. Also, the clocking is quite different, requiring that the clock for the interface be on a gc pin, instead of a dbc/qbc pin (although some pins are both).