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Scholar pedro_uno
Scholar
495 Views
Registered: ‎02-12-2013

clocking wizard alignment of multiple MMCM output clocks with static phase shift

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Hello,

I am using the Clocking Wizard to create an MMCM design to generate clocks.  clkin is and ADC clock running 32MHz. I want to produce two outputs with the MMCM, clkout and clkoutx8.  clkout is the same frequency as clkin and clkoutx8 is eight times that frequency, 256MHz.   I use clkoutx8 to run the dsp pipeline of the system. I need those clocks to be aligned because after receiving the ADC data it is immediately transfered to the faster clock for processing. My part is a ZU2CG.

clkout is clocking the input registers that receive data from the ADC.  I want to be able to add a phase shift on clkout in order to sample the ADC data with good timing margin. 

My problem is that if I put a phase shift on clkout it is no longer aligned with clkoutx8.  I would rather not use two MMCM or use the dynamic phase shift controls to accomplish this. I remember in the past (7-Series?) setting a single phase shift number and having all outputs stay aligned.

Is there a way using Clocking Wizard to set a single phase shift that affects all output clocks, keeping them aligned?

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DSP in hardware and software
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462 Views
Registered: ‎01-22-2015

Re: clocking wizard alignment of multiple MMCM output clocks with static phase shift

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@pedro_uno 

Instead of generating clkout directly from the MMCM, you could generate only clkoutx8 and send it through parallel clock buffers, BUFGCE and BUFGCE_DIV, as shown in Fig 3-49 of UG949(v2019.1). 

Output of the BUFGCE will be clkoutx8.  When programmed to give divide-by-8, output of the BUFGCE_DIV will be ckout.  Outputs of the BUFGCE and the BUFGCE_DIV will be phase-aligned regardless of phase-shift that you assign to the MMCM. 

If for some reason you want to use parallel BUFGCE_DIV with different divider settings, then you must carefully reset and enable the BUFGCE_DIVs as described on page 120 of UG949 – “Otherwise, the divided clocks might become phase shifted from one another in hardware, which is not reported by the Vivado tools.”

Mark

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6 Replies
463 Views
Registered: ‎01-22-2015

Re: clocking wizard alignment of multiple MMCM output clocks with static phase shift

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@pedro_uno 

Instead of generating clkout directly from the MMCM, you could generate only clkoutx8 and send it through parallel clock buffers, BUFGCE and BUFGCE_DIV, as shown in Fig 3-49 of UG949(v2019.1). 

Output of the BUFGCE will be clkoutx8.  When programmed to give divide-by-8, output of the BUFGCE_DIV will be ckout.  Outputs of the BUFGCE and the BUFGCE_DIV will be phase-aligned regardless of phase-shift that you assign to the MMCM. 

If for some reason you want to use parallel BUFGCE_DIV with different divider settings, then you must carefully reset and enable the BUFGCE_DIVs as described on page 120 of UG949 – “Otherwise, the divided clocks might become phase shifted from one another in hardware, which is not reported by the Vivado tools.”

Mark

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Scholar pedro_uno
Scholar
419 Views
Registered: ‎02-12-2013

Re: clocking wizard alignment of multiple MMCM output clocks with static phase shift

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That is a pretty good answer.  It looks like the Clocking Wizard does not know how to do this type of logic.  I will hack into the clock-wiz generated code to make a custom block but it looks low risk.

Thanks

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DSP in hardware and software
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401 Views
Registered: ‎01-22-2015

Re: clocking wizard alignment of multiple MMCM output clocks with static phase shift

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    It looks like the Clocking Wizard does not know how to do this type of logic.
Try telling the Clocking Wizard to use "no buffer" on its output - and then instantiate the BUFGCE and BUFGCE_DIV.
CLK_WIZ_NoBUF.jpg

-a related reminder:

As you do, the MMCM can be used to delay/advance the clock of an FPGA IO interface and place the clock capture-edge in the middle of the data-eye.   When doing this is convenient to place a “set_property PHASESHIFT_MODE LATENCY” constraint on the MMCM, making it easy for us to convert a MMCM phase-shift into a MMCM time-delay/advance (see UG906(v2019.1), pg227).

However, as Avrum warns in <this> post, “PHASESHIFT_MODE LATENCY” should not be used if the MMCM is outputting multiple clocks with a different phase shifts for each clock.  -because, the Vivado tools will incorrectly understand the phase relationship between the clocks, which can sometimes cause timing analysis to be incorrect (eg. for direct clock-crossings).

Mark

 

Scholar pedro_uno
Scholar
373 Views
Registered: ‎02-12-2013

Re: clocking wizard alignment of multiple MMCM output clocks with static phase shift

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I see what you are saying, thanks

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DSP in hardware and software
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Scholar pedro_uno
Scholar
368 Views
Registered: ‎02-12-2013

Re: clocking wizard alignment of multiple MMCM output clocks with static phase shift

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Actually, this won't work for me.  I need to use the slower clock to clock the input registers for the ADC data.  If I multiply by eight then divide by eight the phase will be random, in one of eight possible phase relationships to the input clock.

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DSP in hardware and software
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315 Views
Registered: ‎01-22-2015

Re: clocking wizard alignment of multiple MMCM output clocks with static phase shift

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     If I multiply by eight then divide by eight the phase will be random, in one of eight possible phase relationships to the input clock.

You should get a consistent phase relationship between the MMCM input-clock and the BUFGCE_DIV output-clock if you toggle the CLR pin of the BUFGCE_DIV at the “right” time.  I understand that toggling the CLR pin will reset the divider-counter in the BUFGCE_DIV – although Xilinx documentation is not entirely clear on this.

A “right” time would be on a rising-edge of the MMCM input-clock.  However, dedicated routing from a clock-capable pin to the MMCM may prevent you from using the MMCM input-clock.  Instead, you could configure the MMCM to output both a divide-by-8 and a divide-by-1 version of the input clock.  Then, you could toggle the CLR pin of the BUFGCE_DIV on the rising-edge of the divide-by-1 clock-output of the MMCM.

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