08-08-2019 05:31 AM
I want to use OSERDESE3 on a Zynq Ultrascale+. UG974 page 498 states:
Attribute Type Allowed Values Default Description
ODDR_MODE STRING "FALSE","TRUE" "FALSE" Internal property for Vivado primitive mapping. Do not modify.
So how does one specify whether is DDR or SDR?
08-08-2019 08:19 AM
08-08-2019 09:02 AM
If i presume correctly you have Parallel data (8 bits) synchronous to clock (this clock is CLK_DIV here)
what is DATA_WIDTH attribute set to ?
The OSERDESE3 can serialize an outgoing signal by a 2 or 4 in SDR mode, or by a 4 or 8 in DDR mode. When used with SDR clocking, the DATA_WIDTH attribute is to be set to twice the desired width and data to be transmitted should be applied to two pins at a time
x8 in SDR mode is not supported. follow below table for proper connection and DATA_WIDTH attribute setting
additionlly please refer to OSERDES section of UG571 -. page 165 onward on detailing of OSERDESE3