Re: how to use high speed selectio wizard to captu...

x0276419 · ‎04-06-2018

I have an ADC who has LVDS output interface, the output serial data is coming on Four lanes(DA[3:0]p,DA[3:0]n). And to capture the data frame clock(FRAMECLKp,FRAMECLKn) and data clock (DCLKp,DCLKn) is also given by the device as output in LVDS format.

I am using Ultrascale + FPGA card and VIVADO 2017.4 design suite.

so please tell me how i configure the high speed selectio wizard IP to get deserialized single ended data and clock signals.

thanku,

bruce_karaffa · ‎04-10-2018

Have you read the documentation, UG471 "7 Series FPGAsSelectIO Resources User Guide" and xapp1017 "LVDS Source Synchronous DDR Deserialization"? What have you tried so far? People on the forum will try to help, but we cannot do a design for you..

markgraf · ‎04-10-2018

Check out XAPP524:

https://www.xilinx.com/support/documentation/application_notes/xapp524-serial-lvds-adc-interface.pdf

Steve Markgraf - Distinguished FPGA Design & Support Engineer E5-E
www.designlinxhs.com

zyxer · ‎06-08-2018

Hi,

Did you figure out how to do this?

I understand your question and the documents seems to be lacking (or assuming) certain important mentions.

Now for people who don't read the question properly or don't have implemented themselves, your question may seem silly but actually it is not.

People who want to answer this question should note that this is not about serialization/deserialization. It is about receiving LVDS signals from an ADC into the FPGA using the SelectIO wizard.

The question I have is this. I have an dual 14-bit ADC with 500Mbps with parallel multiplexed LVDS data out. This is a case of no serialization, but only channel multiplexing. The SelectIO wizard (3.2) doesn't seem to have anything integrated to receive such a "parallel" input and also automatically separate out two channels of ADC into two streams. Am I understanding something wrong? OR should I not be using SelectIO at all?

bruce_karaffa · ‎06-10-2018

If you have a two channel, 14 bit ADC with only four data lanes, how can there be no serialization?

zyxer · ‎06-11-2018

Okay.. again, the message wasn't read properly I guess. I don't think I said there are only 4 data lanes. A 14-bit ADC with parallel output will have 14 data lanes and because of LVDS standard, there are actually 14 pairs of data lanes. 4 data lanes was the case of OP, but my case is 14 LVDS lanes (i.e. 14 LVDS pairs).

I want to write down my question again, please read.

Is SlectIO wizard the proper way to interface a dual ADC with parallel LVDS multiplexed output? If so, where are the configuration parameters related to the SelectIO IP?

The input that arrives on the IO pins are as follows (first number is the sample number, second number is the ADC channel number, third number is the bit number) - note - only 3 samples are shown

Line 0 --> ... (s2,c1,b0) ,(s2,c0,b0) ,(s1,c1,b0) ,(s1,c0,b0),(s0,c1,b0) ,(s0,c0,b0)

Line 1 --> ... (s2,c1,b1) ,(s2,c0,b1) ,(s1,c1,b1) ,(s1,c0,b1),(s0,c1,b1) ,(s0,c0,b1)

Line 2 --> ... (s2,c1,b2) ,(s2,c0,b2) ,(s1,c1,b2) ,(s1,c0,b2),(s0,c1,b2) ,(s0,c0,b2)

Line 3 --> ... (s2,c1,b3) ,(s2,c0,b3) ,(s1,c1,b3) ,(s1,c0,b3),(s0,c1,b3) ,(s0,c0,b3)

Line 4 --> ... (s2,c1,b4) ,(s2,c0,b4) ,(s1,c1,b4) ,(s1,c0,b4),(s0,c1,b4) ,(s0,c0,b4)

Line 5 --> ... (s2,c1,b5) ,(s2,c0,b5) ,(s1,c1,b5) ,(s1,c0,b5),(s0,c1,b5) ,(s0,c0,b5)

Line 6 --> ... (s2,c1,b6) ,(s2,c0,b6) ,(s1,c1,b6) ,(s1,c0,b6),(s0,c1,b6) ,(s0,c0,b6)

Line 7 --> ... (s2,c1,b7) ,(s2,c0,b7) ,(s1,c1,b7) ,(s1,c0,b7),(s0,c1,b7) ,(s0,c0,b7)

Line 8 --> ... (s2,c1,b8) ,(s2,c0,b8) ,(s1,c1,b8) ,(s1,c0,b8),(s0,c1,b8) ,(s0,c0,b8)

Line 9 --> ... (s2,c1,b9) ,(s2,c0,b9) ,(s1,c1,b9) ,(s1,c0,b9),(s0,c1,b9) ,(s0,c0,b9)

Line 10 --> ... (s2,c1,b10) ,(s2,c0,b10) ,(s1,c1,b10) ,(s1,c0,b10),(s0,c1,b10) ,(s0,c0,b10)

Line 11 --> ... (s2,c1,b11) ,(s2,c0,b11) ,(s1,c1,b11) ,(s1,c0,b11),(s0,c1,b11) ,(s0,c0,b11)

Line 12 --> ... (s2,c1,b12) ,(s2,c0,b12) ,(s1,c1,b12) ,(s1,c0,b12),(s0,c1,b12) ,(s0,c0,b12)

Line 13 --> ... (s2,c1,b13) ,(s2,c0,b13) ,(s1,c1,b13) ,(s1,c0,b13),(s0,c1,b13) ,(s0,c0,b13)

What I am looking for at the output of the IP:

snapshot of 14-bit wide depth-8 FIFO #0:

{(s2,c0,b13) ,(s2,c0,b12) ,...,(s2,c0,b1) ,(s2,c0,b0)}

{(s1,c0,b13) ,(s1,c0,b12) ,...,(s1,c0,b1) ,(s1,c0,b0)}

{(s0,c0,b13) ,(s0,c0,b12) ,...,(s0,c0,b1) ,(s0,c0,b0)}

empty (yet to be filled)

snapshot of 14-bit wide depth-8 FIFO #1:

{(s2,c1,b13) ,(s2,c1,b12) ,...,(s2,c1,b1) ,(s2,c1,b0)}

{(s1,c1,b13) ,(s1,c1,b12) ,...,(s1,c1,b1) ,(s1,c1,b0)}

{(s0,c1,b13) ,(s0,c1,b12) ,...,(s0,c1,b1) ,(s0,c1,b0)}

empty (yet to be filled)

zyxer · ‎06-11-2018