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dm78
Adventurer
Adventurer
1,108 Views
Registered: ‎03-15-2012

ip update clock validation issue

Hi,

 

i lately switch to 2020.1 for testing (not all changes are noted in the release notes, so give a try) and now i have a very annoying issue.

I'm using the ip integrator with self-packaged ip cores and with 2020.1 i got the following error when updating one of these packaged cores in a block diagram (eg. due to code changes):

ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /video_input_path/smpte_sdi_rx/SDI(100000000) and /sdi_io/AXIS_RX(171875000)
ERROR: [BD 41-237] Bus Interface property FREQ_HZ does not match between /axis_broadcaster_0/S_AXIS(171875000) and /video_input_path/smpte_sdi_rx/SMPTE(100000000)
ERROR: [BD 41-238] Port/Pin property FREQ_HZ does not match between /video_input_path/smpte_sdi_rx/clk(100000000) and /clocks/clock_gen/clk_171M88_o(171875000)

No clock was changed nor is a clock frequency specified on these pins (just auto-derived as in older vivado versions). I can solve it by removing the core and re-add it or by recreating the whole bd via tcl script. But that takes a lot of time everytime and with older vivados i have no issue updating these cores.

I tried to change the pin frequency, but that's a read-only property.

What do i wrong? What can i do (beside recreate or re-add)?

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7 Replies
adrianf00
Adventurer
Adventurer
980 Views
Registered: ‎06-21-2019

I confirm to have the same issue after switching to Vivado 2020.1 from 2019.1.

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andre_schmidt
Participant
Participant
933 Views
Registered: ‎05-16-2018

Any update or solution?

I got the same issue with svereral IP blocks in my design.

Any other solution then delete and insert all IPs?

Thank you!

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df0101
Contributor
Contributor
889 Views
Registered: ‎06-25-2018

I have the same issue using vitis_hls 2020.1 to generate HLS for vivado flow.  When updating the HLS IP block in ip integrator, this clock freq mismatch error pops up at the time of output product generation.  The only solution seems to be remove the block and re-add.  A solution would be helpful as re-wiring and adjusting the s_axilite address map is time consuming and error prone.

 

Thank you!

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df0101
Contributor
Contributor
827 Views
Registered: ‎06-25-2018

Could someone from Xilinx please comment on this?  Is there a workaround to avoid deleting/re-adding the HLS block each time a change is made?

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dm78
Adventurer
Adventurer
682 Views
Registered: ‎03-15-2012

see AR75502

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notAlphaZero
Visitor
Visitor
505 Views
Registered: ‎12-08-2020

I tried the patch and I think it's supposed to change the Freq on the bus from constant but it's not working. I tried the method 1 as recommended. Is there a way to find out that the patch is correctly installed?

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df0101
Contributor
Contributor
354 Views
Registered: ‎06-25-2018

@dm78, Vivado 2020.2 seems to have resolved this issue.

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