low speed clock

[wuyouniyanhu]

How to set a low speed clock of about 1MHz in VIVADO? (Without manual frequency division, used for ILA optional clock domain)

The Clock Wizard page can only select a minimum of 6.25MHz

[pthakare · Accepted solution]

Hi @wuyouniyanhu 

Couple of options here presuming the design is targeted for Ultrascale/Ultrascale+  devices,

#1 Use the MMCM Counter Cascading.
The CLKOUT6 divider (counter) can be cascaded with the CLKOUT4 divider. This provides the capability of an output divider that is larger than 128. The CLKOUT6 counter feeds the input of the CLKOUT4 divider.

If you are using this option, you need to use the override mode to generate all the required 1MHz.

#2 Use the clocking wizard to generate like 7 MHz or 8 MHz and use the BUFGCE_DIV buffer which have dividing capability to divide the clock by "1, 2, 3, 4, 5, 6,
7, 8".

For 7 series MMCM also supports counter cascading and have BUFR clock dividing buffer which also supports division of clock by divide the clock by "1, 2, 3, 4, 5, 6,
7, 8".

BUFGCE_DIV and BUFR  template are available in language template in VIVADO or libraries guide.

[markg@prosensing.com]

-and the methods described by pthakare produce "automatically derived clocks" (see page 90 of UG903(v2019.2)).  That is, Vivado will automatically write a create_generated_clock constraint for the low speed clock that is produced.