My environment is our custom board , one ONSEMI CMOS sensor connected to ZYNQ thru 5-lane LVDS, one lane is for synchronization pattern and others for data. The serialization factor is 10.
I used the reference design of XAPP1017, and slip bits based on training pattern on sync lane, the training pattern is 0x3A6(10 bits). I assumed that when the sync channel has sync-ed, the data lanes should also sync-ed.
We have built more than 50 boards, and there is one board has unsync problem, the phenomenon as below:
1. Most of time, sync lane decoded correct training pattern, some data lanes(randomly) are not (When CMOS is idle, Same training pattern should be there on both sync and data lanes), for example, 0x3A6 decoded from sync lane, but 0x2e9, 0x374, 0x1d3 or some other patterns from data lanes. The captured imaged has vertical stripes.
2. Sometimes when sync lane is OK, training pattern data decoded from data lanes are unstable, keep changing from time to time. Also the image has vertical stripes.
3. And occasionally, even the sync lane cannot sync-ed, and never successfully capture images.
Attachments are the signals captured by ILA for good and fail boards.
Then I started debug process:
1. When I swap the CMOS with good board, the problem still exists. When I swap ZYNQ with good board, the problem goes with ZYNQ
2. I used fixed delay value to control idelay module, and randomly I could find a group of delay values to generate the correct trainning pattern. But when it powered up again, these values did not work at all.
3. I have modified the code to make it possible to slip bits on both sync and data lanes, and enter into sync state-machine only when correct pattern decoded from all the lanes. The test result is there are always some data lanes cannot be sync-ed, and data keep changing.
Now I'm trapped in this, and have to seek for help on forum.