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chlwogns414
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Registered: ‎12-06-2018

porting FPGA global clock in HP bank.

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I am trying to port FPGA global clock in HP bank. 

 

Can it be problem in HD bank when I port FPGA GLOBAL CLOCK in HP BANK? for example, HD bank can't recognize HP bank global clock.

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miker
Xilinx Employee
Xilinx Employee
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Registered: ‎11-30-2007

@chlwogns414 

Sorry, in UltraScale+ the HD I/O Banks have Global Clock inputs but they do not have a XIPHY and CMT (no MMCM/PLLs available).  Therefore, in an HD IO Bank, you can only bring in a clock and drive the global clock buffer.  Please reference the UltraScale Architecture Clocking Resources User Guide (UG572; v1.10; pp 10-11) under Chapter 2: Clocking Resources in section Global Clock Inputs.

I have created a Vivado 2020.2 Zynq UltraScale+ MPSoC XCZU3EG-2SFVC784E Example Design (attached) that highlights how to bring a single-ended clock or a differential clock into an HD IO Bank (IO Bank 26) and drive I/O on another HD IO Bank (IO Bank 24) and an HP IO Bank (IO Bank 66).

forums_usp_hd_clocks.png

Below is the Verilog code.

 

`timescale 1ns / 1ps

module top (
  input  clka,
  input  clkb_p,
  input  clkb_n,
  input  dina,
  input  dinb,
  output douta,
  output doutb
);

  wire clka100;
  wire clkb, clkb100;
  reg [3:0] dina_r = 4'b0;
  reg [3:0] dinb_r = 4'b0;
  
  BUFGCE BUFGCE_clka (
    .I(clka),
    .O(clka100)
  );

  IBUFDS IBUFDS_clkb (
    .I(clkb_p),
    .IB(clkb_n),
    .O(clkb)
  );

  BUFGCE BUFGCE_clkb (
    .I(clkb),
    .O(clkb100)
  );

  always @(posedge clka100)
    dina_r <= {dina_r[2:0], dina};

  assign douta = dina_r[3];
  
  always @(posedge clkb100)
    dinb_r <= {dinb_r[2:0], dinb};

  assign doutb = dinb_r[3];

endmodule

 

Below are the timing constraints.

 

create_clock -name clka100 -period 10.000 [get_ports clka]
create_clock -name clkb100 -period 10.000 [get_ports clkb_p]

 

Below are the physical constraints.

 

# XCZU3EG-2SFVC784E

# HD I/O Bank 26 1.8V
set_property -dict { PACKAGE_PIN F15  IOSTANDARD LVCMOS18 } [get_ports clka]
set_property -dict { PACKAGE_PIN G13  IOSTANDARD LVDS_25  } [get_ports clkb_p]
set_property -dict { PACKAGE_PIN F13  IOSTANDARD LVDS_25  } [get_ports clkb_n]
# HP I/O Bank 66 1.8V
set_property -dict { PACKAGE_PIN G8   IOSTANDARD LVCMOS18 } [get_ports dina]
set_property -dict { PACKAGE_PIN F7   IOSTANDARD LVCMOS18 } [get_ports douta]
# HD I/O Bank 24 3.3V
set_property -dict { PACKAGE_PIN AD15 IOSTANDARD LVCMOS33 } [get_ports dinb]
set_property -dict { PACKAGE_PIN AD14 IOSTANDARD LVCMOS33 } [get_ports doutb]

 

The XCZU3EG-SFVC784 has the following package layout (reference the Zynq UltraScale+ Device Packaging and Pinouts Product Specification User Guide (UG1075; v1.9)).

forums_xczu3egsfvc784_package.png

If you look at the XCZU3EG-SFVC784 package file, you want to make sure you bring single-ended clocks in on a Global Clock "P" side pin and differential clocks in on a Global Clock "P" and "N" pin pair.  I have highlighted HD IO Bank 26 which I used in my example design.  You would want to find the _HDGC_ pins to bring in the global clocks.

 

Pin   Pin Name                            Memory Byte Group  Bank  I/O Type  Super Logic Region 
L13   IO_L12N_AD0N_26                     NA                 26    HD        NA                 
L14   IO_L12P_AD0P_26                     NA                 26    HD        NA                 
J14   IO_L11N_AD1N_26                     NA                 26    HD        NA                 
K14   IO_L11P_AD1P_26                     NA                 26    HD        NA                 
H13   IO_L10N_AD2N_26                     NA                 26    HD        NA                 
H14   IO_L10P_AD2P_26                     NA                 26    HD        NA                 
G14   IO_L9N_AD3N_26                      NA                 26    HD        NA                 
G15   IO_L9P_AD3P_26                      NA                 26    HD        NA                 
E15   IO_L8N_HDGC_AD4N_26                 NA                 26    HD        NA                 
F15   IO_L8P_HDGC_AD4P_26                 NA                 26    HD        NA                 
F13   IO_L7N_HDGC_AD5N_26                 NA                 26    HD        NA                 
G13   IO_L7P_HDGC_AD5P_26                 NA                 26    HD        NA                 
E13   IO_L6N_HDGC_AD6N_26                 NA                 26    HD        NA                 
E14   IO_L6P_HDGC_AD6P_26                 NA                 26    HD        NA                 
D14   IO_L5N_HDGC_AD7N_26                 NA                 26    HD        NA                 
D15   IO_L5P_HDGC_AD7P_26                 NA                 26    HD        NA                 
C13   IO_L4N_AD8N_26                      NA                 26    HD        NA                 
C14   IO_L4P_AD8P_26                      NA                 26    HD        NA                 
A13   IO_L3N_AD9N_26                      NA                 26    HD        NA                 
B13   IO_L3P_AD9P_26                      NA                 26    HD        NA                 
A14   IO_L2N_AD10N_26                     NA                 26    HD        NA                 
B14   IO_L2P_AD10P_26                     NA                 26    HD        NA                 
A15   IO_L1N_AD11N_26                     NA                 26    HD        NA                 
B15   IO_L1P_AD11P_26                     NA                 26    HD        NA                 

 

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miker
Xilinx Employee
Xilinx Employee
689 Views
Registered: ‎11-30-2007

@chlwogns414 

If an external clock enters the FPGA on a Global Clock pin and either drive a global clock buffer (BUFG) or drives an MMCM/PLL followed by a global clock buffer (BUFG), your clock will now be available throughout the device regardless of IO Bank or type of IO Bank (HP or HD).  The key is driving the clock onto a global clock buffer.

  • MRCC/SRCC --> BUFG
  • MRCC/SRCC --> MMCM --> BUFG
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chlwogns414
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Registered: ‎12-06-2018

Do I have to use BUFG even if I used MMCM?

Anyway if I use differential signal in HD bank error comes out even if I drive like below.

  • MRCC/SRCC --> MMCM --> BUFG

could yo tell me the reason why?

 

Thank You

 

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miker
Xilinx Employee
Xilinx Employee
621 Views
Registered: ‎11-30-2007

@chlwogns414 

Sorry, in UltraScale+ the HD I/O Banks have Global Clock inputs but they do not have a XIPHY and CMT (no MMCM/PLLs available).  Therefore, in an HD IO Bank, you can only bring in a clock and drive the global clock buffer.  Please reference the UltraScale Architecture Clocking Resources User Guide (UG572; v1.10; pp 10-11) under Chapter 2: Clocking Resources in section Global Clock Inputs.

I have created a Vivado 2020.2 Zynq UltraScale+ MPSoC XCZU3EG-2SFVC784E Example Design (attached) that highlights how to bring a single-ended clock or a differential clock into an HD IO Bank (IO Bank 26) and drive I/O on another HD IO Bank (IO Bank 24) and an HP IO Bank (IO Bank 66).

forums_usp_hd_clocks.png

Below is the Verilog code.

 

`timescale 1ns / 1ps

module top (
  input  clka,
  input  clkb_p,
  input  clkb_n,
  input  dina,
  input  dinb,
  output douta,
  output doutb
);

  wire clka100;
  wire clkb, clkb100;
  reg [3:0] dina_r = 4'b0;
  reg [3:0] dinb_r = 4'b0;
  
  BUFGCE BUFGCE_clka (
    .I(clka),
    .O(clka100)
  );

  IBUFDS IBUFDS_clkb (
    .I(clkb_p),
    .IB(clkb_n),
    .O(clkb)
  );

  BUFGCE BUFGCE_clkb (
    .I(clkb),
    .O(clkb100)
  );

  always @(posedge clka100)
    dina_r <= {dina_r[2:0], dina};

  assign douta = dina_r[3];
  
  always @(posedge clkb100)
    dinb_r <= {dinb_r[2:0], dinb};

  assign doutb = dinb_r[3];

endmodule

 

Below are the timing constraints.

 

create_clock -name clka100 -period 10.000 [get_ports clka]
create_clock -name clkb100 -period 10.000 [get_ports clkb_p]

 

Below are the physical constraints.

 

# XCZU3EG-2SFVC784E

# HD I/O Bank 26 1.8V
set_property -dict { PACKAGE_PIN F15  IOSTANDARD LVCMOS18 } [get_ports clka]
set_property -dict { PACKAGE_PIN G13  IOSTANDARD LVDS_25  } [get_ports clkb_p]
set_property -dict { PACKAGE_PIN F13  IOSTANDARD LVDS_25  } [get_ports clkb_n]
# HP I/O Bank 66 1.8V
set_property -dict { PACKAGE_PIN G8   IOSTANDARD LVCMOS18 } [get_ports dina]
set_property -dict { PACKAGE_PIN F7   IOSTANDARD LVCMOS18 } [get_ports douta]
# HD I/O Bank 24 3.3V
set_property -dict { PACKAGE_PIN AD15 IOSTANDARD LVCMOS33 } [get_ports dinb]
set_property -dict { PACKAGE_PIN AD14 IOSTANDARD LVCMOS33 } [get_ports doutb]

 

The XCZU3EG-SFVC784 has the following package layout (reference the Zynq UltraScale+ Device Packaging and Pinouts Product Specification User Guide (UG1075; v1.9)).

forums_xczu3egsfvc784_package.png

If you look at the XCZU3EG-SFVC784 package file, you want to make sure you bring single-ended clocks in on a Global Clock "P" side pin and differential clocks in on a Global Clock "P" and "N" pin pair.  I have highlighted HD IO Bank 26 which I used in my example design.  You would want to find the _HDGC_ pins to bring in the global clocks.

 

Pin   Pin Name                            Memory Byte Group  Bank  I/O Type  Super Logic Region 
L13   IO_L12N_AD0N_26                     NA                 26    HD        NA                 
L14   IO_L12P_AD0P_26                     NA                 26    HD        NA                 
J14   IO_L11N_AD1N_26                     NA                 26    HD        NA                 
K14   IO_L11P_AD1P_26                     NA                 26    HD        NA                 
H13   IO_L10N_AD2N_26                     NA                 26    HD        NA                 
H14   IO_L10P_AD2P_26                     NA                 26    HD        NA                 
G14   IO_L9N_AD3N_26                      NA                 26    HD        NA                 
G15   IO_L9P_AD3P_26                      NA                 26    HD        NA                 
E15   IO_L8N_HDGC_AD4N_26                 NA                 26    HD        NA                 
F15   IO_L8P_HDGC_AD4P_26                 NA                 26    HD        NA                 
F13   IO_L7N_HDGC_AD5N_26                 NA                 26    HD        NA                 
G13   IO_L7P_HDGC_AD5P_26                 NA                 26    HD        NA                 
E13   IO_L6N_HDGC_AD6N_26                 NA                 26    HD        NA                 
E14   IO_L6P_HDGC_AD6P_26                 NA                 26    HD        NA                 
D14   IO_L5N_HDGC_AD7N_26                 NA                 26    HD        NA                 
D15   IO_L5P_HDGC_AD7P_26                 NA                 26    HD        NA                 
C13   IO_L4N_AD8N_26                      NA                 26    HD        NA                 
C14   IO_L4P_AD8P_26                      NA                 26    HD        NA                 
A13   IO_L3N_AD9N_26                      NA                 26    HD        NA                 
B13   IO_L3P_AD9P_26                      NA                 26    HD        NA                 
A14   IO_L2N_AD10N_26                     NA                 26    HD        NA                 
B14   IO_L2P_AD10P_26                     NA                 26    HD        NA                 
A15   IO_L1N_AD11N_26                     NA                 26    HD        NA                 
B15   IO_L1P_AD11P_26                     NA                 26    HD        NA                 

 

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