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wrxue
Observer
Observer
867 Views
Registered: ‎09-19-2019

why can't i get the same simulation result of rfdc ip example design

I just tried to use the example design in PG269 page135. 

But my simulation waveform is different from that

Block DesignBlock DesignsimulationsimulationWhat can i do?

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klumsde
Moderator
Moderator
798 Views
Registered: ‎04-18-2011

In this case are you forcing the real signal onto the ADC input. 

Go to the imports directory in the example project and look for the file that does all this it's something like **nano_seq** this is the file where the testbench manages the sequencer and the stimulus 

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wrxue
Observer
Observer
774 Views
Registered: ‎09-19-2019

Hello, klumsde.

I am not sure about what you mean.

There is a *nano_seq* module in testbench.

After I open the design example, I didn't change any thing and just run the simulation.

simulation filesimulation file

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klumsde
Moderator
Moderator
740 Views
Registered: ‎04-18-2011

Hi @wrxue 

Can you be a bit clearer? Are you saying that the simulation you are running is just the example design test bench? 

If so how long do you run it for. What is the output of the console? 


 

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wrxue
Observer
Observer
723 Views
Registered: ‎09-19-2019

Hello, @klumsde 

I indeed run the test bench of example design without changing anything.

I realized the simulation time is not long enough(1000ns).

So I extended it to 1000us.

The result is followed.

simulation result of example designsimulation result of example designsimulation result of example designsimulation result of example design

I expect to see the wave of ADC or DAC is like the simulated wave in PG269 (v2.1).

ADC wave in PG269 v2.1ADC wave in PG269 v2.1DAC wave in PG269 v2.1DAC wave in PG269 v2.1

And the console message is below.

launch_simulation
WARNING: [Memdata 28-176] There are no bmm files or elf files. Therefore Vivado could not produce any .mem files. Check the design for the existence of processors and associated elf files.
INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/wrxue/VivadoProject/usp_rf_data_converter_1_ex/usp_rf_data_converter_1_ex.sim/sim_1/behav/xsim'
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [SIM-utils-50] Design contains embedded sources, generating MEM files for simulation...
WARNING: [Memdata 28-176] There are no bmm files or elf files. Therefore Vivado could not produce any .mem files. Check the design for the existence of processors and associated elf files.
INFO: [SIM-utils-54] Inspecting design source files for 'demo_tb' in fileset 'sim_1'...
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/wrxue/VivadoProject/usp_rf_data_converter_1_ex/usp_rf_data_converter_1_ex.sim/sim_1/behav/xsim'
xvlog --incr --relax -L smartconnect_v1_0 -prj demo_tb_vlog.prj
xvhdl --incr --relax -prj demo_tb_vhdl.prj
INFO: [USF-XSim-69] 'compile' step finished in '1' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/wrxue/VivadoProject/usp_rf_data_converter_1_ex/usp_rf_data_converter_1_ex.sim/sim_1/behav/xsim'
xelab -wto 9a2f971d8d854358beb7fcb3f9af32f9 --incr --debug typical --relax --mt 8 -L xilinx_vip -L xil_defaultlib -L xpm -L xlconstant_v1_1_6 -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L unisims_ver -L unimacro_ver -L secureip --snapshot demo_tb_behav xil_defaultlib.demo_tb xil_defaultlib.glbl -log elaborate.log
Vivado Simulator 2019.1
Copyright 1986-1999, 2001-2019 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2019.1/bin/unwrapped/lnx64.o/xelab -wto 9a2f971d8d854358beb7fcb3f9af32f9 --incr --debug typical --relax --mt 8 -L xilinx_vip -L xil_defaultlib -L xpm -L xlconstant_v1_1_6 -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L smartconnect_v1_0 -L unisims_ver -L unimacro_ver -L secureip --snapshot demo_tb_behav xil_defaultlib.demo_tb xil_defaultlib.glbl -log elaborate.log 
Using 8 slave threads.
Starting static elaboration
Completed static elaboration
INFO: [XSIM 43-4323] No Change in HDL. Linking previously generated obj files to create kernel
run_program: Time (s): cpu = 00:00:25 ; elapsed = 00:00:25 . Memory (MB): peak = 7826.797 ; gain = 0.000 ; free physical = 14611 ; free virtual = 25548
INFO: [USF-XSim-69] 'elaborate' step finished in '25' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in '/home/wrxue/VivadoProject/usp_rf_data_converter_1_ex/usp_rf_data_converter_1_ex.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
   with args "demo_tb_behav -key {Behavioral:sim_1:Functional:demo_tb} -tclbatch {demo_tb.tcl} -protoinst "protoinst_files/bd_a15e.protoinst" -protoinst "protoinst_files/rfdc_ex.protoinst" -view {/home/wrxue/VivadoProject/usp_rf_data_converter_1_ex/demo_tb_behav.wcfg} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2019.1
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/bd_a15e.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//m00_exit_pipeline/m00_exit/M_AXI
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//m00_exit_pipeline/m00_exit/S_AXI
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//m00_exit_pipeline/m_axi
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//m00_exit_pipeline/s_axi
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//m00_sc2axi/M_AXI
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//m01_exit_pipeline/m01_exit/M_AXI
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//m01_exit_pipeline/m01_exit/S_AXI
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//m01_exit_pipeline/m_axi
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//m01_exit_pipeline/s_axi
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//m01_sc2axi/M_AXI
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//m02_exit_pipeline/m02_exit/M_AXI
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//m02_exit_pipeline/m02_exit/S_AXI
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//m02_exit_pipeline/m_axi
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//m02_exit_pipeline/s_axi
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//m02_sc2axi/M_AXI
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//s00_axi2sc/S_AXI
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//s00_entry_pipeline/m_axi
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//s00_entry_pipeline/s00_mmu/M_AXI
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//s00_entry_pipeline/s00_mmu/S_AXI
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//s00_entry_pipeline/s00_si_converter/M_AXI
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//s00_entry_pipeline/s00_si_converter/S_AXI
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//s00_entry_pipeline/s00_transaction_regulator/M_AXI
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//s00_entry_pipeline/s00_transaction_regulator/S_AXI
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/smartconnect_0/inst//s00_entry_pipeline/s_axi
INFO: [Wavedata 42-565] Reading protoinst file protoinst_files/rfdc_ex.protoinst
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i//adc_sink_i/s00
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i//adc_sink_i/s_axi
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i//dac_source_i/m00
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i//dac_source_i/s_axi
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i//smartconnect_0/M00_AXI
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i//smartconnect_0/M01_AXI
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i//smartconnect_0/M02_AXI
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i//smartconnect_0/S00_AXI
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i//usp_rf_data_converter_1/m00_axis
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i//usp_rf_data_converter_1/s00_axis
INFO: [Wavedata 42-564]   Found protocol instance at /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i//usp_rf_data_converter_1/s_axi
Time resolution is 1 ps
open_wave_config /home/wrxue/VivadoProject/usp_rf_data_converter_1_ex/demo_tb_behav.wcfg
source demo_tb.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
#   if { [llength [get_objects]] > 0} {
#     add_wave /
#     set_property needs_save false [current_wave_config]
#   } else {
#      send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
#   }
# }
# run 1000us
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
T=           0: Xilinx RF AMS Demo Testbench.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. demo_tb.dut_and_data_i.DUT.usp_rf_data_converter_1_ex_i.adc_sink_i.inst.ds_slice_00.genblk1.exdes_xpm_mem_ds_i.xpm_mem_ds_wrap2_i.xpm_mem_dg_sdpram_wrap_i.Ixpm_memory_tdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/adc_sink_i/inst/ds_slice_00/genblk1.exdes_xpm_mem_ds_i/xpm_mem_ds_wrap2_i/xpm_mem_dg_sdpram_wrap_i/Ixpm_memory_tdpram/xpm_memory_base_inst/Initial290_31  File: /opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv
Info: [XPM_MEMORY 20-2] MEMORY_INIT_FILE (none), MEMORY_INIT_PARAM together specify no memory initialization. Initial memory contents will be all 0's. demo_tb.dut_and_data_i.DUT.usp_rf_data_converter_1_ex_i.dac_source_i.inst.dg_slice_00.xpm_mem_dg_wrap2_i.xpm_mem_dg_sdpram_wrap_i.Ixpm_memory_tdpram.xpm_memory_base_inst.config_drc  0
Time: 1 ps  Iteration: 0  Process: /demo_tb/dut_and_data_i/DUT/usp_rf_data_converter_1_ex_i/dac_source_i/inst/dg_slice_00/xpm_mem_dg_wrap2_i/xpm_mem_dg_sdpram_wrap_i/Ixpm_memory_tdpram/xpm_memory_base_inst/Initial290_91  File: /opt/Xilinx/Vivado/2019.1/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv
T=              335100: Delay of         40 cycles requested.
T=      755100: Accelerate SIM startup
T=      905100 D=      905100 (ps): AXI WRITE: AxiAddr=0x00004100, Decode H= 2 L=   64, Data=0x00000001  DCC0_SUPPLY_DETECTION_TIMER_ADDR       
T=     1095100 D=      190000 (ps): AXI WRITE: AxiAddr=0x00008100, Decode H= 4 L=   64, Data=0x00000001  DCC1_SUPPLY_DETECTION_TIMER_ADDR       
T=     1315100 D=      220000 (ps): AXI WRITE: AxiAddr=0x0000c100, Decode H= 6 L=   64, Data=0x00000001  DCC2_SUPPLY_DETECTION_TIMER_ADDR       
T=     1505100 D=      190000 (ps): AXI WRITE: AxiAddr=0x00010100, Decode H= 8 L=   64, Data=0x00000001  DCC3_SUPPLY_DETECTION_TIMER_ADDR       
T=     1695100 D=      190000 (ps): AXI WRITE: AxiAddr=0x00014100, Decode H=10 L=   64, Data=0x00000001  ACC0_SUPPLY_DETECTION_TIMER_ADDR       
T=     1915100 D=      220000 (ps): AXI WRITE: AxiAddr=0x00018100, Decode H=12 L=   64, Data=0x00000001  ACC1_SUPPLY_DETECTION_TIMER_ADDR       
T=     2105100 D=      190000 (ps): AXI WRITE: AxiAddr=0x0001c100, Decode H=14 L=   64, Data=0x00000001  ACC2_SUPPLY_DETECTION_TIMER_ADDR       
T=     2295100 D=      190000 (ps): AXI WRITE: AxiAddr=0x00020100, Decode H=16 L=   64, Data=0x00000001  ACC3_SUPPLY_DETECTION_TIMER_ADDR       
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
T=     2325100: Run state machine configuration stage.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
T=     2515100 D=      220000 (ps): AXI WRITE: AxiAddr=0x00014008, Decode H=10 L=    2, Data=0x00000001  ACC0_RESTART_STATE_START_ADDR          
T=     2705100 D=      190000 (ps): AXI WRITE: AxiAddr=0x00014004, Decode H=10 L=    1, Data=0x00000001  ACC0_RESTART_REGISTER_ADDR             
T=     2895100 D=      190000 (ps): AXI WRITE: AxiAddr=0x00004008, Decode H= 2 L=    2, Data=0x00000001  DCC0_RESTART_STATE_START_ADDR          
T=     3115100 D=      220000 (ps): AXI WRITE: AxiAddr=0x00004004, Decode H= 2 L=    1, Data=0x00000001  DCC0_RESTART_REGISTER_ADDR             
T=     3145100: Wait for the serial tile configuration to complete before configuring core.
T=     3145100: This is true once all POR tiles have left stage 0.
T=     4305100: Tile 02 has reached its end state of 00000000
T=     4685100: Tile 03 has reached its end state of 00000000
T=    14945100: Tile 06 has reached its end state of 0000000f
T=    15325100: Tile 07 has reached its end state of 0000000f
T=    15705100: Tile 00 has reached its end state of 00000001
T=    16085100: Tile 01 has reached its end state of 0000000f
T=    17605100: Tile 05 has reached its end state of 0000000f
T=    20265100: Tile 04 has reached its end state of 00000001
T=    21405100: ADC configuration
T=    21575100 D=    21575100 (ps): AXI READ : Address=0x000161c4, Decode H=11 L=  113, Data=0x000001f1                                         
T=    21845100 D=    18730000 (ps): AXI WRITE: AxiAddr=0x000161c4, Decode H=11 L=  113, Data=0x000001d1                                         
T=    22065100 D=      490000 (ps): AXI READ : Address=0x000165c4, Decode H=11 L=  369, Data=0x000001f9                                         
T=    22335100 D=      490000 (ps): AXI WRITE: AxiAddr=0x000165c4, Decode H=11 L=  369, Data=0x000001d9                                         
T=    22815100: DAC configuration
Writing data to channel 0 memory
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
T=   226475100: Run state machine until clocks are enabled.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
T=   226635100 D=   204300000 (ps): AXI WRITE: AxiAddr=0x00014008, Decode H=10 L=    2, Data=0x00000108  ACC0_RESTART_STATE_START_ADDR          
T=   226825100 D=      190000 (ps): AXI WRITE: AxiAddr=0x00014004, Decode H=10 L=    1, Data=0x00000001  ACC0_RESTART_REGISTER_ADDR             
T=   227045100 D=      220000 (ps): AXI WRITE: AxiAddr=0x00004008, Decode H= 2 L=    2, Data=0x00000108  DCC0_RESTART_STATE_START_ADDR          
T=   227235100 D=      190000 (ps): AXI WRITE: AxiAddr=0x00004004, Decode H= 2 L=    1, Data=0x00000001  DCC0_RESTART_REGISTER_ADDR             
T=   228045100: Tile 01 has reached its end state of 0000000f
T=   228425100: Tile 02 has reached its end state of 00000000
T=   228805100: Tile 03 has reached its end state of 00000000
T=   229565100: Tile 05 has reached its end state of 0000000f
T=   229945100: Tile 06 has reached its end state of 0000000f
T=   230325100: Tile 07 has reached its end state of 0000000f
T=   327985100: Tile 00 has reached its end state of 00000008
T=   332545100: Tile 04 has reached its end state of 00000008
Enabling channel 0 memory
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
T=   334455100: Run DAC state machine until end stage.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
T=   334615100 D=   107380000 (ps): AXI WRITE: AxiAddr=0x00004008, Decode H= 2 L=    2, Data=0x0000080f  DCC0_RESTART_STATE_START_ADDR          
T=   334835100 D=      220000 (ps): AXI WRITE: AxiAddr=0x00004004, Decode H= 2 L=    1, Data=0x00000001  DCC0_RESTART_REGISTER_ADDR             
T=   335625100: Tile 01 has reached its end state of 0000000f
T=   336005100: Tile 02 has reached its end state of 00000000
T=   336385100: Tile 03 has reached its end state of 00000000
T=   344365100: Tile 00 has reached its end state of 0000000f
T=   345505100: Sending tone at 50.000000 MHz to DAC00.
INSTANCE demo_tb.dut_and_data_i.dac_sink.tile_sink_0_i.ds_slice_0_1.fft_checker_wrapper_i.dac_fft_checker_i :max_tone_level detected = 512.107713, tone_threshold set = 51.210771
INSTANCE $unit_demo_tb_axi4l_nano_seq_sv.tonePredPassFail :tonePredict.mag_tones 50000000.000000 Hz
INSTANCE $unit_demo_tb_axi4l_nano_seq_sv.tonePredPassFail :tonePredict.mag_tones 6350000000.000000 Hz
INSTANCE $unit_demo_tb_axi4l_nano_seq_sv.tonePredPassFail :toneResults.mag_tones 50000000.000000 Hz
INSTANCE $unit_demo_tb_axi4l_nano_seq_sv.tonePredPassFail :toneResults.mag_tones 6350000000.000000 Hz
INSTANCE $unit_demo_tb_axi4l_nano_seq_sv.tonePredPassFail :**************************************************************************************
INSTANCE $unit_demo_tb_axi4l_nano_seq_sv.tonePredPassFail :tonePredPassFail = PASS, error = 0, i_tone_match = 1, q_tone_match = 1, mag_tone_match 1
INSTANCE $unit_demo_tb_axi4l_nano_seq_sv.tonePredPassFail :**************************************************************************************
INSTANCE demo_tb.dut_and_data_i.dac_sink.tile_sink_0_i.ds_slice_0_1.fft_checker_wrapper_i.dac_fft_checker_i :tonePredPassFail TEST PASSED
       ----->> DAC00 Analog range = 0.500 @         14bit = 14627.7 codes (89.3%)
       ----->> DAC00 AXI-Stream range =       65462
SIM-SPEEDUP DAC TILE =           0 disabled
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
T=   349395100: Run ADC state machine until end stage.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
T=   349565100 D=    14730000 (ps): AXI WRITE: AxiAddr=0x00014008, Decode H=10 L=    2, Data=0x0000080b  ACC0_RESTART_STATE_START_ADDR          
T=   349755100 D=      190000 (ps): AXI WRITE: AxiAddr=0x00014004, Decode H=10 L=    1, Data=0x00000001  ACC0_RESTART_REGISTER_ADDR             
T=   349785100: Sending tone at 3.906250 MHz to ADC00.
T=   352295100: Tile 05 has reached its end state of 0000000f
T=   352675100: Tile 06 has reached its end state of 0000000f
T=   353055100: Tile 07 has reached its end state of 0000000f
T=   364075100: Tile 04 has reached its end state of 0000000b
Capturing channel 0 to memory
T=           366035100: Delay of        200 cycles requested.
T=   368785100 D=    19030000 (ps): AXI WRITE: AxiAddr=0x00014008, Decode H=10 L=    2, Data=0x00000003  ACC0_RESTART_STATE_START_ADDR          
T=   369005100 D=      220000 (ps): AXI WRITE: AxiAddr=0x00014004, Decode H=10 L=    1, Data=0x00000001  ACC0_RESTART_REGISTER_ADDR             
Reading channel 0 capture memory
Reading channel 1 capture memory
Performing FFT on channel 0 capture memory data
INSTANCE demo_tb.dut_and_data_i.adc_sink_i.ds_slice_00.fft_checker_wrapper_i.adc_fft_checker_i_i :max_tone_level detected = 453.153962, tone_threshold set = 113.288491
INSTANCE $unit_demo_tb_axi4l_nano_seq_sv.tonePredPassFail :tonePredict.mag_tones 3906000.000000 Hz
INSTANCE $unit_demo_tb_axi4l_nano_seq_sv.tonePredPassFail :tonePredict.mag_tones 1996094000.000000 Hz
INSTANCE $unit_demo_tb_axi4l_nano_seq_sv.tonePredPassFail :toneResults.mag_tones 3906250.000000 Hz
INSTANCE $unit_demo_tb_axi4l_nano_seq_sv.tonePredPassFail :toneResults.mag_tones 1996093750.000000 Hz
INSTANCE $unit_demo_tb_axi4l_nano_seq_sv.tonePredPassFail :**************************************************************************************
INSTANCE $unit_demo_tb_axi4l_nano_seq_sv.tonePredPassFail :tonePredPassFail = PASS, error = 0, i_tone_match = 1, q_tone_match = 1, mag_tone_match 1
INSTANCE $unit_demo_tb_axi4l_nano_seq_sv.tonePredPassFail :**************************************************************************************
INSTANCE demo_tb.dut_and_data_i.adc_sink_i.ds_slice_00.fft_checker_wrapper_i.adc_fft_checker_i_i :tonePredPassFail TEST PASSED
<<-----        ADC0_01 Analog range = 0.522 @         12bit = 3817.2 codes (93.2%)
<<-----        ADC00 AXI-Stream range =       57976
T=           645985100: Delay of         20 cycles requested.
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
** Test Passed
** Test completed successfully
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
$stop called at time : 646205100 ps : File "/home/wrxue/VivadoProject/usp_rf_data_converter_1_ex/imports/demo_tb_axi4l_nano_seq.sv" Line 460
run: Time (s): cpu = 00:02:09 ; elapsed = 00:17:08 . Memory (MB): peak = 7826.797 ; gain = 0.000 ; free physical = 12384 ; free virtual = 23296
xsim: Time (s): cpu = 00:02:10 ; elapsed = 00:17:13 . Memory (MB): peak = 7826.797 ; gain = 0.000 ; free physical = 12379 ; free virtual = 23292
INFO: [USF-XSim-96] XSim completed. Design snapshot 'demo_tb_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000us
launch_simulation: Time (s): cpu = 00:02:38 ; elapsed = 00:17:41 . Memory (MB): peak = 7826.797 ; gain = 0.000 ; free physical = 12379 ; free virtual = 23292

 

 

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klumsde
Moderator
Moderator
646 Views
Registered: ‎04-18-2011

Hi @wrxue 

It seems to be working to me. 

When I look at the console the testbench is checking the tone it received matches the expected frequency and finds that it is. 

Keith 

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