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337247537@qq.com
Observer
Observer
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Registered: ‎04-02-2015

使用PLL+selected io解码cameralink数据

我们自己做的ZYNQ板卡,来解码cameralink相机数据。由于IO管脚不够的原因,我们在FPGA外部没有加入解码芯片()。所以使用PLL+selected io  IP来解码传感器数据。解码后的视频数据通过VDMA写入DDR,然后通过VDMA读出后发送给到FPGA外部mipi(tc358746)芯片。

 当FPGA温度低于70度时一切功能正常,当FPGA温度高于70度时,MIPI接收端开始报告MIPI时序错误。此时如果关闭cameralink解码锁相环(复位锁相环),MIPI时序错误随即消失。我们怀疑是解码cameralink的锁相环工作会影响FPGA 输出给MIPI芯片的并行信号,从而导致接收端报告MIPI时序错误。

 请问FPGA做cameralink解码为什么会导致这种现象

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337247537@qq.com
Observer
Observer
192 Views
Registered: ‎04-02-2015

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karnanl
Xilinx Employee
Xilinx Employee
129 Views
Registered: ‎03-30-2016

Hello 337247537@qq.com 

Just curios ....
1. Are your sensor sending MIPI D-PHY signal ? are you building a custom IP to receive sensor MIPI IP ?
2. If Camera is sending signal with Camera-Link standard, I believe Xilinx does not have Camera-link IP. (Only XAPP to implement 7:1 deserialization )


Kind regards
Leo


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