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Registered: ‎09-16-2020

7-series 2 lane MIPI D-PHY DSI

Hey everyone,

I am still trying to wrap my head around how to deal with MIPI and how someone can chime in.  I know the IP core is out there and free now (I think) so that's a good start.  I am still relatively new to FPGAs and using them so that's why I am asking probably basic questions here.  I have a few FPGA boards around here to play with (MOJO - Spartan 7, Arty7-35T, Another board that starts with Mach (not your board obviously)) and some SBC that I can play with (Rpi, BB, Jetson) want to try to get a feel on how to get moving on this. 

This is a question/recommendation on how people handle this with the small displays.  I know phones and everyone go this route so there is stuff out there.  I have found a few options. 

1.) FPGA to take some data (HDMI, LVDS, RGB) and convert that to the MIPI

2.) Use a bridge to do one step for me.  I seen some that do HDMI to MIPI, MIPI to FPGA, Parallel to MIPI.  I worked at one place that dealt with SERDES to handle images and output but not sure if that applied here in the MIPI world or not or if that is a different standard. 

3.) Use an application processor to do the MIPI for me. 

My issue is that stuff is all over the place and I need to keep cost and development in mind.  I don't want to reinvent the wheel or framework here so the FPGA core seems appealing.  Say I did want to use the Arty board to do a MIPI test and example.  Where is a good place to start on that?  I believe that the Xilinx is able to do simulations so maybe a test image that I try to transmit and simulate would be the way to go?

I see this video out there from 5 years ago:

I see there are a lot of resources on the UltraScale line but that is a bit overkill for what I am looking to do both in processing and cost.  Is there a certain number of Logic Cells and Memory I have to keep an eye out for?

Sorry this is the buck shot approach but I just can't see the clear way that people handle this like a lot of other technologies.  


This video covers a brief overview of MIPI and Xilinx MIPI solutions along with how to find more information on the D-PHY MIPI solutions available with Xilin...
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Xilinx Employee
Xilinx Employee
Registered: ‎03-30-2016

Hello @gregtronics 

Please see also PG232 Chapter 5.
Xilinx has a simple MIPI application example that include MIPI DSI TX Subsystem IP.
This application example available for UltraScale+ (ZCU102 board) and Artix-7 (SP701 board).


Please generate the design , this example should be a good referece for your design.
# Please note that Xilinx MIPI IPs do not support UltraScale devices.

Kind regards


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