06-11-2013 03:03 AM
I have a problem when I generate a bitstream of my model. (the target device is a spartan 6 -> 6slx150fgg676-2)
The error is :
Pack:2310 - Too many comps of type "DSP48A1" found to fit this device. New map ERROR Map:237 - The design is too large to fit the device. Please check the Design Summary section to see
My model occupies only 6 or 7% of the number of slices registers but my model need 250 DSPA and the spartan6 have only 180 DSPA.
How can i do ? Why the synthesis tool not uses others slice registers to do DSP ?
Thank you :)
06-11-2013 04:16 AM
this may be a problem of your source code.
e.g. if you are using some generate statement to instantiate DSP48 blocks the synthesis tool can't help but try to use these blocks.
Only if the synthesis tool has the choice to infer DSP48 blocks it may use logic ressouces instead if necessary.
Have a nie synthesis
06-11-2013 04:27 AM
Thank you for you answer
I use system generator with Simulink and in my model i don't have a specific DSP48 block.
Blocks that i use are : ConstantMultiplier, Constant, Delay, AddSub, Multiplier, Relationnal, Mux, cast (convert).
06-11-2013 07:41 AM
How wide are your datapaths? What is your clock rate? Sample rates?
You need to think about which blocks may be using DSP slices and where you have room to make tradeoffs to use less of them.
For example, if you have a very large timing budget for a specific path, you could simply check the box to use Fabric resources instead of DSP slices (many sysgen blocks have this option).
You could also re-architect your design to re-use DSP resources.
I hope you see the point that there are many factors that contribute to DSP slice usage and how to solve this problem depends wholly on your design.