11-13-2019 07:32 AM
I am a little confused about the TDATA pixel mapping when trasmitting video data over AXI4-Stream interface. Below are two chunks of two different documents, where the descriptions are kinda opposite to one another:
The first one is more recent and states that the active data bits should be MSB aligned.
According to the second document the data should be LSB aligned.
Which configuration should be considered correct?
11-13-2019 07:48 AM
The Xilinx video IPs are following the UG934. Please consider it as the most up to date.
11-15-2019 05:33 AM
Updated: I have aksed the section "Video IP: AXI Feature Adoption" to be removed from UG1037. This should just point to UG934 which is kept up to date