cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Observer
Observer
4,131 Views
Registered: ‎03-11-2016

AXI-Stream to Video Out and Video In to AXI-Stream

Hello all,

I have been trying to convert the AVNET core into RGB and some video processing. However, I would like to access cores I have written before for the video out.

 

So, my goal is:

Avnet HDMI IN => Video In to AXI-4 Stream => Chroma Resample => YCbCr to RGB => Video4-Stream to Video out => (My Cores) => Video4-Stream to Video In => RGB to YCbCr => ...

 

So everything works if I do this:

Avnet HDMI IN => Video In to AXI-4 Stream => Chroma Resample => YCbCr to RGB => RGB to YCbCr => ...

 

However, when I added the Video4-Stream to Video out core and Video4-Stream to Video In core, things seem to fail. I am unsure why tho. The design looks like such:

setup.png

 

Some tip and guidance is appreciated, as I'm unclear on how to solve such an issue.

0 Kudos
Reply
11 Replies
Moderator
Moderator
4,104 Views
Registered: ‎11-09-2015

Hi @chanyeoh,

 

How do you check that it is working in this case Avnet HDMI IN => Video In to AXI-4 Stream => Chroma Resample => YCbCr to RGB => RGB to YCbCr => ...?

And why do you say that it is not working in the other case?

 

What I usually check when I have issue in a video design:

-> Check the underflow/overflow signals of Video In to AXI-4 Stream

-> Add an ILA to see if there are some change on the tready and tvalid signals

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Reply
Observer
Observer
4,086 Views
Registered: ‎03-11-2016

Hello,

I was able to check it when I compiled to whole project and run it. Everything ran properly.

 

When I check the underflow/overflow signals of Video In to AXI-4 Stream they are both 0.

When I check the ILA I do see changes from the tvalid signal. tready is always set to 1.

 

I have also checked the video active signals, and it turns out to be the same as the tvalid signal. However, for some reason, the video is not being shown/framing correctly.

 

0 Kudos
Reply
Moderator
Moderator
4,081 Views
Registered: ‎11-09-2015

Hi @chanyeoh,

 

What do you use to display the video? Do you have data at the output of the design?

 

Thanks and Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Reply
Observer
Observer
4,079 Views
Registered: ‎03-11-2016

Hello,

On the output side, it appears to underflow, and the video is not locked. The HSync, VSync and Video Active are also not active. I wonder why is such the case.

0 Kudos
Reply
Moderator
Moderator
4,066 Views
Registered: ‎11-09-2015

Hi @chanyeoh,

 

Continu to use an ILA on the upstream blocks to understand why


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Reply
Observer
Observer
4,047 Views
Registered: ‎03-11-2016

 
0 Kudos
Reply
Observer
Observer
4,046 Views
Registered: ‎03-11-2016

Hi,

I have finally manged to get some output. However, I am unable to understand the underflow. It seems to be the same width as the inactive frame. Why would such behavior happen? Does that mean I have to use VDMA?setup.png

0 Kudos
Reply
Moderator
Moderator
4,033 Views
Registered: ‎11-09-2015

Hi @chanyeoh,

 

It happens because you are running at the same frequency input and output. So each time you have data available, they are sent out directly.

 

Yes using a VDMA to do frame buffering can help.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Reply
Observer
Observer
4,026 Views
Registered: ‎03-11-2016

What if I want to avoid VDMA? Is there any way to avoid it? What would happen if I ran the output frequency 0.1 MHz slower? Would it resolve the issue.

0 Kudos
Reply
Moderator
Moderator
3,049 Views
Registered: ‎11-09-2015

Hi @chanyeoh

 

Yes I guess that if your output frequency is slightly below you won't see the underflow. But I would reduce the frequency by at least 1MHz.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Reply
Moderator
Moderator
2,981 Views
Registered: ‎11-09-2015

Hi @chanyeoh,

 

Any updates on this issue? Is it solved? If yes please close the thread marking it as solved.

 

Kind Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Reply